公开(公告)号：US20070229147A1

公开(公告)日：2007-10-04

申请号：US11395475

申请日：2006-03-30

申请人： Bruce Doyle ,  Manish Kumar ,  John Wuu ,  Samuel Naffziger

发明人： Bruce Doyle ,  Manish Kumar ,  John Wuu ,  Samuel Naffziger

IPC分类号： G05F1/10

CPC分类号： G05F1/46

摘要： For one disclosed embodiment, a supply voltage regulator is to control voltage at a first supply node for a circuit. The supply voltage regulator includes one or more first devices to couple the first supply node to a second supply node when the circuit is in a predetermined operational state and includes an error sensor to control the one or more first devices. The supply voltage regulator includes one or more second devices to couple the first supply node to a third supply node when the circuit is in the predetermined operational state. Other embodiments are also disclosed.

摘要翻译： 对于一个公开的实施例，电源电压调节器用于控制电路的第一供电节点处的电压。 电源电压调节器包括一个或多个第一器件，用于当电路处于预定操作状态时将第一电源节点耦合到第二电源节点，并且包括用于控制一个或多个第一器件的误差传感器。 电源稳压器包括一个或多个第二设备，用于当电路处于预定操作状态时将第一供电节点耦合到第三供电节点。 还公开了其他实施例。

公开(公告)号：US20190067152A1

公开(公告)日：2019-02-28

申请号：US15686558

申请日：2017-08-25

申请人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

发明人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC分类号： H01L23/367 ,  H01L25/065 ,  H01L25/00

摘要： Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US20060265174A1

公开(公告)日：2006-11-23

申请号：US11132055

申请日：2005-05-18

申请人： Bruce Doyle ,  Samuel Naffziger ,  Christopher Poirier ,  James Ignowski

发明人： Bruce Doyle ,  Samuel Naffziger ,  Christopher Poirier ,  James Ignowski

IPC分类号： G01K1/00

CPC分类号： G01K7/015 ,  G01K1/026 ,  H01L23/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thermal sensing system may comprise a plurality of remote sensors distributed across an integrated circuit (IC). Each of the plurality of remote sensors provides an analog signal that varies as a function of temperature of a respective region of the IC where each respective remote sensor is located. A central system, forming part of the IC, samples the analog signals from the plurality of remote sensors and converts the sampled analog signals to corresponding digital values.

摘要翻译： 热感测系统可以包括分布在集成电路（IC）上的多个远程传感器。 多个远程传感器中的每一个提供模拟信号，该模拟信号作为每个相应远程传感器所在的IC的相应区域的温度的函数而变化。 构成IC的一部分的中央系统对来自多个远程传感器的模拟信号进行采样，并将采样的模拟信号转换成相应的数字值。

公开(公告)号：US10431517B2

公开(公告)日：2019-10-01

申请号：US15686558

申请日：2017-08-25

申请人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

发明人： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC分类号： H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H01L23/36 ,  H01L23/373

摘要： Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US07447919B2

公开(公告)日：2008-11-04

申请号：US10818974

申请日：2004-04-06

申请人： Steven F. Liepe ,  Samuel Naffziger

发明人： Steven F. Liepe ,  Samuel Naffziger

IPC分类号： G06F1/00 ,  G06F11/00

CPC分类号： H03K19/0008 ,  G06F11/00

摘要： Techniques are disclosed for increasing reliability of an integrated circuit. In one embodiment, an integrated circuit includes core chip circuitry. The integrated circuit includes means for increasing a power supply voltage V provided to the core chip circuitry, such as by increasing the voltage V to a maximum value. The integrated circuit also includes means for identifying a clock frequency F for which F

摘要翻译： 公开了用于增加集成电路的可靠性的技术。 在一个实施例中，集成电路包括核心芯片电路。 集成电路包括用于增加提供给核心芯片电路的电源电压V的装置，例如通过将电压V增加到最大值。 集成电路还包括用于识别其中C是开关电容的时钟频率F的装置，其中P < max 是核心芯片电路的预定最大功耗。 集成电路还包括用于向电路提供具有频率F的时钟信号的装置。

公开(公告)号：US20060279343A1

公开(公告)日：2006-12-14

申请号：US11152274

申请日：2005-06-13

申请人： Samuel Naffziger

发明人： Samuel Naffziger

IPC分类号： H03K3/356

CPC分类号： H03K3/0375 ,  H03K3/356104

摘要： In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. A low-pass filter is placed between the output of a forward inverter and the inputs of a feedback keeper. The first and second outputs of the low-pass filter are connected to first and second inputs respectively of the feedback keeper. The only type of diffusion connected to the first output of the low-pass filter is a P-type diffusion. The only type of diffusion connected to the second output of the low-pass filter is an N-type diffusion. The feedback keeper is connected to an input of the forward inverter.

摘要翻译： 在优选实施例中，本发明提供了用于减少锁存器中的软错误事件的电路和方法。 在正向逆变器的输出端和反馈保持器的输入端之间放置一个低通滤波器。 低通滤波器的第一和第二输出分别连接到反馈保持器的第一和第二输入端。 连接到低通滤波器的第一输出的唯一类型的扩散是P型扩散。 连接到低通滤波器的第二输出的唯一类型的扩散是N型扩散。 反馈控制器连接到正向逆变器的输入。

公开(公告)号：US20060248367A1

公开(公告)日：2006-11-02

申请号：US11118600

申请日：2005-04-29

申请人： Timothy Fischer ,  Samuel Naffziger ,  Benjamin Patella

发明人： Timothy Fischer ,  Samuel Naffziger ,  Benjamin Patella

IPC分类号： G06F1/12

CPC分类号： G06F1/12

摘要： Systems and methods for implementing count calibration for synchronous data transfer between clock domains are disclosed. An exemplary system may include a count calibration circuit for determining latency between an early clock domain and a late clock domain. The system may also include a data path configurable for synchronous data transfer between clock domains based at least in part on the latency.

摘要翻译： 公开了用于实现时钟域之间同步数据传输的计数校准的系统和方法。 示例性系统可以包括用于确定早期时钟域和后期时钟域之间的等待时间的计数校准电路。 系统还可以包括至少部分地基于等待时间来配置用于时钟域之间的同步数据传输的数据路径。

公开(公告)号：US20060069928A1

公开(公告)日：2006-03-30

申请号：US10951179

申请日：2004-09-27

申请人： Bradley Winick ,  Samuel Naffziger

发明人： Bradley Winick ,  Samuel Naffziger

IPC分类号： G06F1/26

CPC分类号： G06F1/305

摘要： Systems, methodologies, media, and other embodiments associated with detecting and responding to a degradation of a direct current provided to a frequency scalable processor are described. One exemplary frequency scalable processor includes a voltage regulating logic configured to request that a direct current having a reference voltage be provided to the processor. The example processor may also include a logic for detecting whether the voltage matches the reference voltage to within a desired tolerance and to selectively store processor state and/or data based on the detecting.

公开(公告)号：US20050223251A1

公开(公告)日：2005-10-06

申请号：US10818974

申请日：2004-04-06

申请人： Steven Liepe ,  Samuel Naffziger

发明人： Steven Liepe ,  Samuel Naffziger

IPC分类号： G06F1/26 ,  G06F1/28 ,  G06F11/00

CPC分类号： H03K19/0008 ,  G06F11/00

摘要： Techniques are disclosed for increasing reliability of an integrated circuit. In one embodiment, an integrated circuit includes core chip circuitry. The integrated circuit includes means for increasing a power supply voltage V provided to the core chip circuitry, such as by increasing the voltage V to a maximum value. The integrated circuit also includes means for identifying a clock frequency F for which F

摘要翻译： 公开了用于增加集成电路的可靠性的技术。 在一个实施例中，集成电路包括核心芯片电路。 集成电路包括用于增加提供给核心芯片电路的电源电压V的装置，例如通过将电压V增加到最大值。 该集成电路还包括用于识别其中C是开关电容的时钟频率F的装置，其中，P＆lt; P＆lt; max 是核心芯片电路的预定最大功耗。 集成电路还包括用于向电路提供具有频率F的时钟信号的装置。

公开(公告)号：US20050050494A1

公开(公告)日：2005-03-03

申请号：US10653328

申请日：2003-09-02

申请人： Tyson McGuffin ,  Thomas Chen ,  Samuel Naffziger ,  Eric Fetzer

发明人： Tyson McGuffin ,  Thomas Chen ,  Samuel Naffziger ,  Eric Fetzer

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5022 ,  G06F2217/78

摘要： Systems and methods are provided that can be utilized to estimate power associated with a circuit design. The estimated power is determined by employing power characterizations to determine power consumption associated with non-conventional circuits in the circuit design. The power characterizations can be determined prior to circuit design timing analysis, stored and utilized during circuit design timing analysis. The power estimates associated with the non-conventional circuits can be added to power estimates associated with the conventional circuits of the circuit design to compute a power associated with the circuit design.

摘要翻译： 提供了可用于估计与电路设计相关联的功率的系统和方法。 通过使用功率特征来确定在电路设计中与非常规电路相关联的功率消耗来确定估计功率。 功率特征可以在电路设计时序分析之前确定，在电路设计时序分析期间存储和利用。 与非常规电路相关联的功率估计可以被添加到与电路设计的常规电路相关联的功率估计，以计算与电路设计相关联的功率。