公开(公告)号：US06266730B1

公开(公告)日：2001-07-24

申请号：US09507303

申请日：2000-02-18

申请人： Donald V. Perino ,  Billy Wayne Garrett, Jr. ,  Haw-Jyh Liaw ,  David Nguyen ,  Srinivas Nimmagadda ,  James A. Gasbarro ,  Richard DeWitt Crisp

发明人： Donald V. Perino ,  Billy Wayne Garrett, Jr. ,  Haw-Jyh Liaw ,  David Nguyen ,  Srinivas Nimmagadda ,  James A. Gasbarro ,  Richard DeWitt Crisp

IPC分类号： H05K102

CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

摘要： A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.

摘要翻译： 尽管在模块和连接器上使用了总线，但高频总线系统确保高保真信号的均匀到达时间到高频总线上的设备。 高频总线系统包括具有连接在第一和第二端之间的一个或多个设备的第一总线段。 第一总线段具有用于传播高频信号的至少一对传输线，并且该装置耦合到该对传输线。 高频总线系统还包括没有与其连接的设备的第二总线段。 第二总线段还具有用于传播高频信号的至少一对传输线。 第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本相同的时间被引入第二总线段的第一端时，它们到达每一个 设备在大致相同的时间连接到第一总线段。 而且，当两个信号在基本相同的时间起始于连接到第一总线段的设备时，它们在几乎相同的时间到达第二总线段的第一端。 尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在分段中的路由选择，并且尽管信息类型（例如地址，数据）也是均匀到达时间 或控制，由信号携带。

公开(公告)号：US6067594A

公开(公告)日：2000-05-23

申请号：US938084

申请日：1997-09-26

申请人： Donald V. Perino ,  Billy Wayne Garrett, Jr. ,  Haw-Jyh Liaw ,  David Nguyen ,  Srinivas Nimmagadda ,  James A. Gasbarro ,  Richard DeWitt Crisp

发明人： Donald V. Perino ,  Billy Wayne Garrett, Jr. ,  Haw-Jyh Liaw ,  David Nguyen ,  Srinivas Nimmagadda ,  James A. Gasbarro ,  Richard DeWitt Crisp

IPC分类号： G06F13/00 ,  G06F13/40 ,  G11C5/00 ,  G11C5/06 ,  H05K1/02 ,  H05K1/14 ,  H05K7/14

CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  H05K1/0246 ,  H05K1/0248 ,  H05K7/1459 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

摘要： A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.

摘要翻译： 尽管在模块和连接器上使用了总线，但高频总线系统确保高保真信号的均匀到达时间到高频总线上的设备。 高频总线系统包括具有连接在第一和第二端之间的一个或多个设备的第一总线段。 第一总线段具有用于传播高频信号的至少一对传输线，并且该装置耦合到该对传输线。 高频总线系统还包括没有与其连接的设备的第二总线段。 第二总线段还具有用于传播高频信号的至少一对传输线。 第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本相同的时间被引入第二总线段的第一端时，它们到达每一个 设备在大致相同的时间连接到第一总线段。 而且，当两个信号在基本相同的时间起始于连接到第一总线段的设备时，它们在几乎相同的时间到达第二总线段的第一端。 尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在分段中的路由选择，并且尽管信息类型（例如地址，数据）也是均匀到达时间 或控制，由信号携带。

公开(公告)号：US20090210604A1

公开(公告)日：2009-08-20

申请号：US12426083

申请日：2009-04-17

申请人： Haw-Jyh Liaw ,  David Nguyen

发明人： Haw-Jyh Liaw ,  David Nguyen

IPC分类号： G06F13/14

CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

摘要： A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line.

摘要翻译： 存储器模块包括用于承载第一信号的第一信号线。 第一信号线具有（i）沿着存储器模块的长度设置并耦合到终端的第一线段，以及（ii）沿着存储器模块的宽度设置并耦合到边缘指状物的第二线段。 第一线段和第二线段在转弯处耦合在一起。 第一同步存储器件和第二同步存储器件耦合到第一线段。 第一信号以顺序的方式到达第一同步存储器件和第二同步存储器件。 存储器模块包括沿着第一信号线路线路由的时钟线。 时钟信号沿着沿着第一信号线的第一信号沿着顺序到达第一同步存储器件和第二同步存储器件。

公开(公告)号：US07523244B2

公开(公告)日：2009-04-21

申请号：US11459858

申请日：2006-07-25

申请人： Haw-Jyh Liaw ,  David Nguyen

发明人： Haw-Jyh Liaw ,  David Nguyen

IPC分类号： G06F13/42

CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

摘要： A memory module includes a first signal line to carry a first signal that enters the module at a first end of the first signal line and a second signal line to carry a second signal that enters the module at a first end of the second signal line. The module includes a first memory device disposed on a first side of the module and a second memory module disposed on a second side of the module positioned opposite to the first side. The first memory device and the second memory device are connected to the first signal line and the second signal line. The first signal and the second signal traverse alongside each other to arrive in turn at the first memory device and the second memory device.

摘要翻译： 存储器模块包括：第一信号线，用于承载在第一信号线的第一端进入模块的第一信号;以及第二信号线，用于承载在第二信号线的第一端进入模块的第二信号。 模块包括设置在模块的第一侧上的第一存储器件和设置在与第一侧相对定位的模块的第二侧上的第二存储器模块。 第一存储器件和第二存储器件连接到第一信号线和第二信号线。 第一信号和第二信号彼此并行地依次移动以在第一存储器件和第二存储器件上依次进入。

公开(公告)号：US07085872B2

公开(公告)日：2006-08-01

申请号：US09839768

申请日：2001-04-19

申请人： Haw-Jyh Liaw ,  David Nguyen

发明人： Haw-Jyh Liaw ,  David Nguyen

IPC分类号： H05K1/02

CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

摘要： A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.

公开(公告)号：US07870322B2

公开(公告)日：2011-01-11

申请号：US12426083

申请日：2009-04-17

申请人： Haw-Jyh Liaw ,  David Nguyen

发明人： Haw-Jyh Liaw ,  David Nguyen

IPC分类号： G06F13/42

CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

摘要： A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line.

摘要翻译： 存储器模块包括用于承载第一信号的第一信号线。 第一信号线具有（i）沿着存储器模块的长度设置并耦合到终端的第一线段，以及（ii）沿着存储器模块的宽度设置并耦合到边缘指状物的第二线段。 第一线段和第二线段在转弯处耦合在一起。 第一同步存储器件和第二同步存储器件耦合到第一线段。 第一信号以顺序的方式到达第一同步存储器件和第二同步存储器件。 存储器模块包括沿着第一信号线路线路由的时钟线。 时钟信号沿着沿着第一信号线的第一信号沿着顺序到达第一同步存储器件和第二同步存储器件。

公开(公告)号：US07523247B2

公开(公告)日：2009-04-21

申请号：US11683916

申请日：2007-03-08

申请人： Haw-Jyh Liaw ,  David Nguyen

发明人： Haw-Jyh Liaw ,  David Nguyen

IPC分类号： G06F13/42

CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

摘要： A memory module includes a signal line to carry a signal that traverses the signal line until reaching a termination at an end of the signal line. The module includes a clock line to carry a clock signal that traverses the clock line alongside the signal until the signal reaches a second termination at an end of the clock line. The module includes a first memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the first memory device at substantially the same time. The module includes a second memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the second memory device at substantially the same time and after the signal and the clock signal arrive at the first memory device.

摘要翻译： 存储器模块包括用于承载穿过信号线的信号的信号线，直到在信号线的末端达到终止。 该模块包括一个时钟线，用于携带沿信号旁边穿过时钟线的时钟信号，直到信号在时钟线的末端达到第二个终止。 模块包括连接到信号线和时钟线的第一存储器件，使得信号和时钟信号在基本相同的时间到达第一存储器件。 模块包括连接到信号线和时钟线的第二存储器件，使得信号和时钟信号在基本上相同的时间到达第二存储器件并且在信号和时钟信号到达第一存储器件之后。

公开(公告)号：US20070150635A1

公开(公告)日：2007-06-28

申请号：US11681390

申请日：2007-03-02

申请人： Haw-Jyh Liaw ,  David Nguyen

发明人： Haw-Jyh Liaw ,  David Nguyen

IPC分类号： G06F13/14 ,  G11C5/06

CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

摘要： A memory system includes a first signal line to carry a first signal that enters the module at a first end of the first signal line and a second signal line to carry a second signal that enters the module at a first end of the second signal line. The module includes a first memory device disposed on a first side of the module and a second memory module disposed on a second side of the module positioned opposite to the first side. The first memory device and the second memory device are connected to the first signal line and the second signal line. The first signal and the second signal traverse alongside each other to arrive in turn at the first memory device and the second memory device. The system may include a controller that provides the first signal and the second signal.

摘要翻译： 存储器系统包括：第一信号线，用于承载在第一信号线的第一端进入模块的第一信号;以及第二信号线，用于承载在第二信号线的第一端进入模块的第二信号。 模块包括设置在模块的第一侧上的第一存储器件和设置在与第一侧相对定位的模块的第二侧上的第二存储器模块。 第一存储器件和第二存储器件连接到第一信号线和第二信号线。 第一信号和第二信号彼此并行地依次移动以在第一存储器件和第二存储器件上依次进入。 该系统可以包括提供第一信号和第二信号的控制器。

公开(公告)号：US20050246471A9

公开(公告)日：2005-11-03

申请号：US09839768

申请日：2001-04-19

申请人： Haw-Jyh Liaw ,  David Nguyen

发明人： Haw-Jyh Liaw ,  David Nguyen

IPC分类号： G06F13/00 ,  G06F13/40 ,  G11C5/00 ,  G11C5/06 ,  H05K1/02 ,  H05K1/14 ,  H05K7/14

CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

摘要： A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.

摘要翻译： 尽管在模块和连接器上使用了总线，但高频总线系统确保高保真信号的均匀到达时间到高频总线上的设备。 高频总线系统包括具有连接在第一和第二端之间的一个或多个设备的第一总线段。 第一总线段具有用于传播高频信号的至少一对传输线，并且该装置耦合到该对传输线。 高频总线系统还包括没有与其连接的设备的第二总线段。 第二总线段还具有用于传播高频信号的至少一对传输线。 第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本相同的时间被引入第二总线段的第一端时，它们到达每一个 设备在大致相同的时间连接到第一总线段。 而且，当两个信号在基本相同的时间起始于连接到第一总线段的设备时，它们在几乎相同的时间到达第二总线段的第一端。 尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在分段中的路由选择，并且尽管信息类型（例如地址，数据）也是均匀到达时间 或控制，由信号携带。

公开(公告)号：US20110090727A1

公开(公告)日：2011-04-21

申请号：US12975313

申请日：2010-12-21

申请人： Haw-Jyh Liaw ,  David Nguyen

发明人： Haw-Jyh Liaw ,  David Nguyen

IPC分类号： G11C5/02

CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

摘要： A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line.

摘要翻译： 存储器模块包括用于承载第一信号的第一信号线。 第一信号线具有（i）沿着存储器模块的长度设置并耦合到终端的第一线段，以及（ii）沿着存储器模块的宽度设置并耦合到边缘指状物的第二线段。 第一线段和第二线段在转弯处耦合在一起。 第一同步存储器件和第二同步存储器件耦合到第一线段。 第一信号以顺序的方式到达第一同步存储器件和第二同步存储器件。 存储器模块包括沿着第一信号线路线路由的时钟线。 时钟信号沿着沿着第一信号线的第一信号沿着顺序到达第一同步存储器件和第二同步存储器件。