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    Direct plane attachment for capacitors
    1.
    发明授权
    Direct plane attachment for capacitors 有权
    电容直接平面贴装

    公开(公告)号：US06608257B1

    公开(公告)日：2003-08-19

    申请号：US10021769

    申请日：2001-12-12

    申请人： Valerie St. Cyr ,  Istvan Novak

    发明人： Valerie St. Cyr ,  Istvan Novak

    IPC分类号： H05K102

    CPC分类号： H05K1/186 ,  H05K1/0231 ,  H05K1/183 ,  H05K3/3442 ,  H05K2201/09309 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913

    摘要： A method of direct plane attachment of capacitors is disclosed. In one embodiment, a printed circuit board (PCB) having a signal layer, a first conductive plane, and a second conductive plane is provided. The signal layer may be the outermost layer of the PCB, while the first conductive layer may be arranged between the signal layer and the second conductive layer. A cavity may be formed in the printed circuit board, wherein the cavity extends from the signal layer down to the first conductive plane. The cavity may be large enough to accommodate one or more capacitors. A first terminal of the capacitor may be attached to the first conductive plane. The second terminal of the capacitor may be mounted within an opening in the first conductive plane. The method may allow a bypass capacitor to be directly coupled to a power or reference plane.

    摘要翻译： 公开了一种直接平面连接电容器的方法。 在一个实施例中，提供了具有信号层，第一导电平面和第二导电平面的印刷电路板（PCB）。 信号层可以是PCB的最外层，而第一导电层可以布置在信号层和第二导电层之间。 空腔可以形成在印刷电路板中，其中空腔从信号层向下延伸到第一导电平面。 空腔可以足够大以容纳一个或多个电容器。 电容器的第一端子可以附接到第一导电平面。 电容器的第二端子可以安装在第一导电平面内的开口内。 该方法可以允许旁路电容器直接耦合到功率或参考平面。

    Method and apparatus to manufacture an electronic package with direct wiring pattern
    3.
    发明授权
    Method and apparatus to manufacture an electronic package with direct wiring pattern 失效
    制造具有直接布线图案的电子封装的方法和装置

    公开(公告)号：US06459039B1

    公开(公告)日：2002-10-01

    申请号：US09597906

    申请日：2000-06-19

    申请人： Raschid J. Bezama ,  Govindarajan Natarajan ,  Robert W. Pasco

    发明人： Raschid J. Bezama ,  Govindarajan Natarajan ,  Robert W. Pasco

    IPC分类号： H05K102

    CPC分类号： H01L23/49827 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/113 ,  H05K3/3436 ,  H05K2201/09836 ,  H05K2201/10378 ,  Y02P70/613 ,  H01L2224/0401

    摘要： An electronic package assembly for electrical interconnection between two electronic modules having differing conductive array parameters is disclosed. The electronic package assembly includes two electronic modules, providing between the two electronic modules an interposer having a top surface and a bottom surface; a first set of conductive arrays having a first conductive array parameter on the top surface, and a second set of conductive arrays having a second conductive array parameter on the bottom surface, the second conductive array and the first conductive array having differing parameters. A plurality of conductors traverses a thickness of the interposer of the electronic package assembly, with the conductors including a conductive material optionally coated with a dielectric material, the conductors having a first end at the first conductive arrays and a second end at the second conductive arrays, whereby the conductors connecting the first and second conductive arrays therein are adapted to spatially transform the differing parameters to provide an electrical interconnection. A conductive matrix surrounds the conductors of the interposer of the electronic package assembly. The first set of conductive arrays includes the same conductive array parameters as a first electronic module and the second set of conductive arrays includes the same conductive array parameters as a second electronic module.

    摘要翻译： 公开了一种用于具有不同导电阵列参数的两个电子模块之间的电互连的电子封装组件。 电子封装组件包括两个电子模块，在两个电子模块之间提供具有顶表面和底表面的插入件; 具有在顶表面上具有第一导电阵列参数的第一组导电阵列和在底表面上具有第二导电阵列参数的第二组导电阵列，所述第二导电阵列和第一导电阵列具有不同的参数。 多个导体横穿电子封装组件的插入件的厚度，其中导体包括任选涂覆有电介质材料的导电材料，导体在第一导电阵列处具有第一端，在第二导电阵列处具有第二端 由此连接其中的第一和第二导电阵列的导体适于空间转换不同的参数以提供电互连。 导电矩阵围绕电子封装组件的插入件的导体。 第一组导电阵列包括与第一电子模块相同的导电阵列参数，第二组导电阵列包括与第二电子模块相同的导电阵列参数。

    High-frequency bus system
    4.
    发明授权
    High-frequency bus system 失效
    高频总线系统

    公开(公告)号：US06266730B1

    公开(公告)日：2001-07-24

    申请号：US09507303

    申请日：2000-02-18

    申请人： Donald V. Perino ,  Billy Wayne Garrett, Jr. ,  Haw-Jyh Liaw ,  David Nguyen ,  Srinivas Nimmagadda ,  James A. Gasbarro ,  Richard DeWitt Crisp

    发明人： Donald V. Perino ,  Billy Wayne Garrett, Jr. ,  Haw-Jyh Liaw ,  David Nguyen ,  Srinivas Nimmagadda ,  James A. Gasbarro ,  Richard DeWitt Crisp

    IPC分类号： H05K102

    CPC分类号： G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

    摘要： A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.

    摘要翻译： 尽管在模块和连接器上使用了总线，但高频总线系统确保高保真信号的均匀到达时间到高频总线上的设备。 高频总线系统包括具有连接在第一和第二端之间的一个或多个设备的第一总线段。 第一总线段具有用于传播高频信号的至少一对传输线，并且该装置耦合到该对传输线。 高频总线系统还包括没有与其连接的设备的第二总线段。 第二总线段还具有用于传播高频信号的至少一对传输线。 第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本相同的时间被引入第二总线段的第一端时，它们到达每一个 设备在大致相同的时间连接到第一总线段。 而且，当两个信号在基本相同的时间起始于连接到第一总线段的设备时，它们在几乎相同的时间到达第二总线段的第一端。 尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在分段中的路由选择，并且尽管信息类型（例如地址，数据）也是均匀到达时间 或控制，由信号携带。

    Printed substrate board
    5.
    发明授权
    Printed substrate board 失效
    印刷基板

    公开(公告)号：US06531660B2

    公开(公告)日：2003-03-11

    申请号：US09754659

    申请日：2001-01-04

    申请人： Atsushi Ono

    发明人： Atsushi Ono

    IPC分类号： H05K102

    CPC分类号： H05K3/0052 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2203/1545 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T428/15 ,  Y10T428/24314

    摘要： A printed substrate board constructed, from a substantially unitary body includes at least one edge part along a side mountable into an external mounting device. The printed board includes individual board bodies having a shape that is out of parallel with the edge part. The individual board bodies have at least one portion of an opposing side joined to the edge parts through a secondary part. The secondary parts, combined with the individual board bodies, are substantially parallel with the edge parts and allow simple separation of each board body from the printed board along cutting boundary portions while enabling simplified orientation for later assembly.

    摘要翻译： 从基本上整体的主体构造的印刷基板包括沿着可安装到外部安装装置的一侧的至少一个边缘部分。 印刷板包括具有与边缘部分不平行的形状的单独的板主体。 单独的板体具有通过次级部分连接到边缘部分的相对侧的至少一部分。 与单独的板体结合的次要部件基本上与边缘部分平行，并且允许每个板主体与切割边界部分沿着印刷电路板简单分离，同时能够简化定向以便稍后组装。

    Film used as a substrate for integrated circuits
    8.
    发明授权
    Film used as a substrate for integrated circuits 有权
    薄膜用作集成电路的基板

    公开(公告)号：US06420660B1

    公开(公告)日：2002-07-16

    申请号：US09445235

    申请日：1999-12-08

    申请人： Veronika Sauer ,  Ben Slager ,  Friedrich Lach ,  Alfred Bauer ,  Horst Hartmann ,  Günter Kolodzei

    发明人： Veronika Sauer ,  Ben Slager ,  Friedrich Lach ,  Alfred Bauer ,  Horst Hartmann ,  Günter Kolodzei

    IPC分类号： H05K102

    CPC分类号： H05K3/0097 ,  G06K19/077 ,  G06K19/07743 ,  H01L23/49855 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K3/202 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/2009 ,  H05K2203/1545 ,  H01L2924/00

    摘要： The chips for chip cards are customarily provided on a film strip which consists of a synthetic foil and a conductor track pattern and are connected to the conductor track pattern by way of bonding wires. Automatic mounting is made possible by the use of a film strip with periodically arranged conductor track patterns. For chips which can be driven via contacts as well as in a contactless manner, using a coil, conductor tracks are effectively provided on both sides of the synthetic foil forming the film strip. However, the film strip then becomes very inflexible so that it cannot be suitably handled by conventional automatic apparatus. The invention proposes to provide the metal foils wherefrom the conductor tracks are cut out with additional interruptions which reduce the cross-section of the metal foils at short intervals in the direction perpendicular to the longitudinal direction of the film. The film strip thus becomes more flexible so that it can be handled by conventional automatic apparatus.

    摘要翻译： 用于芯片卡的芯片通常设置在由合成箔和导体轨迹图案组成的薄膜条上，并且通过接合线连接到导体轨迹图案。 通过使用具有周期性布置的导体轨迹图案的胶片条，可实现自动安装。 对于可以通过触点驱动的芯片以及以非接触方式驱动的芯片，使用线圈，在形成薄膜条的合成箔的两侧上有效地设置导体轨迹。 然而，薄膜条变得非常不灵活，使得它不能被传统的自动装置适当地处理。 本发明提出提供金属箔，其中导体轨迹被切除，附加中断，其在垂直于膜的纵向方向的方向上以短的间隔减小金属箔的横截面。 因此，薄膜条变得更加柔软，从而可以通过常规的自动装置来处理。

    Circuit board for preventing solder failures
    10.
    发明授权
    Circuit board for preventing solder failures 失效
    用于防止焊料故障的电路板

    公开(公告)号：US06222135B1

    公开(公告)日：2001-04-24

    申请号：US09176653

    申请日：1998-10-21

    申请人： Yukiko Daido ,  Yoshihisa Hatta

    发明人： Yukiko Daido ,  Yoshihisa Hatta

    IPC分类号： H05K102

    CPC分类号： H05K1/0271 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/34 ,  H05K3/3405 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2201/10446 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49165

    摘要： A circuit board (10) on which surface electronic components (15) are mounted during a reflow process comprises a circuit portion (12), a surrounding circumferential portion (13) and at least one elongated opening (14) formed in the surrounding circumferential portion substantially parallel to the direction the board travels during the reflow direction (16) to prevent electronic component soldering failures that may occur as a result of the deflection of the circuit board flow process.

    摘要翻译： 在回流处理期间，其上安装表面电子部件（15）的电路板（10）包括电路部分（12），周围圆周部分（13）和形成在周围圆周部分中的至少一个细长开口（14） 基本上平行于板在回流方向（16）行进的方向，以防止由于电路板流动过程的偏转而可能发生的电子部件焊接故障。