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    MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    磁记忆体装置及其制造方法

    公开(公告)号：US20130032910A1

    公开(公告)日：2013-02-07

    申请号：US13251461

    申请日：2011-10-03

    申请人： Dong Ha Jung ,  Ki Seon Park ,  Guk Cheon Kim

    发明人： Dong Ha Jung ,  Ki Seon Park ,  Guk Cheon Kim

    IPC分类号： H01L29/82 ,  H01L21/8246

    CPC分类号： G11C11/161 ,  H01L43/08

    摘要： A magnetic memory device includes a first fixing layer, a first tunnel barrier coupled to the first fixing layer, a free layer coupled to the first tunnel barrier and having a stacked structure including a first ferromagnetic layer, an oxide tunnel spacer, and a second ferromagnetic layer, a second tunnel barrier coupled to the free layer, and a second fixing layer coupled to the second tunnel barrier.

    摘要翻译： 磁存储器件包括第一固定层，耦合到第一固定层的第一隧道势垒层，耦合到第一隧道势垒的自由层，并且具有包括第一铁磁层，氧化物隧道衬垫和第二铁磁层 层，耦合到自由层的第二隧道势垒，以及耦合到第二隧道势垒的第二固定层。

    Metal line of semiconductor device without production of high resistance compound due to metal diffusion and method for forming the same
    5.
    发明授权
    Metal line of semiconductor device without production of high resistance compound due to metal diffusion and method for forming the same 失效
    由于金属扩散而不生产高电阻化合物的半导体器件的金属线及其形成方法

    公开(公告)号：US08159069B2

    公开(公告)日：2012-04-17

    申请号：US12940521

    申请日：2010-11-05

    申请人： Baek Mann Kim ,  Seung Jin Yeom ,  Dong Ha Jung ,  Jeong Tae Kim

    发明人： Baek Mann Kim ,  Seung Jin Yeom ,  Dong Ha Jung ,  Jeong Tae Kim

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76856

    摘要： A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and includes a WNx layer, a W—N—B ternary layer, and a Ti—N—B ternary layer. A wetting layer is formed on the diffusion barrier and is made of one of a Ti layer or a TiN layer. An upper metal line is formed on the wetting layer to fill the metal line forming region of the insulation layer.

    摘要翻译： 金属线包括形成在半导体衬底上的下金属线。 在具有下金属线的半导体衬底上形成绝缘层，并且在绝缘层中限定暴露下金属线的至少一部分的金属线形成区域。 在绝缘层的金属线形成区域的表面上形成扩散阻挡层，其包括WNx层，W-N-B三元层和Ti-N-B三元层。 在扩散阻挡层上形成润湿层，由Ti层或TiN层之一构成。 在润湿层上形成上金属线以填充绝缘层的金属线形成区域。

    MRAM Fabrication Method with Sidewall Cleaning
    9.
    发明申请
    MRAM Fabrication Method with Sidewall Cleaning 有权
    MRAM制造方法与侧壁清洁

    公开(公告)号：US20130267042A1

    公开(公告)日：2013-10-10

    申请号：US13443818

    申请日：2012-04-10

    申请人： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

    发明人： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

    IPC分类号： H01L21/02

    CPC分类号： H01L27/222 ,  H01L43/12

    摘要： Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

    摘要翻译： 描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。