公开(公告)号：US20110242412A1

公开(公告)日：2011-10-06

申请号：US13028491

申请日：2011-02-16

申请人： Dong Han Lee ,  Jong Ho Roh

发明人： Dong Han Lee ,  Jong Ho Roh

IPC分类号： H04N5/04

CPC分类号： G06F3/1438 ,  G06F3/1446 ,  G09G5/12

摘要： The display controller includes a decoder, a control circuit, and a video output logic circuit. The decoder is configured to decode a first display command and output a decoding signal and first synchronizing information indicating the first display command is received. The control circuit is configured to generate a first control signal based on second synchronizing information and the decoding signal. The second synchronizing information is output from a second display controller and indicates a second display command is received. The video output logic circuit is configured to send a part of video data stored in a video source and a plurality of first timing control signals for displaying the part of the video data on a display to the display based on the first control signal.

摘要翻译： 显示控制器包括解码器，控制电路和视频输出逻辑电路。 解码器被配置为对第一显示命令进行解码并输出解码信号，并且接收到表示第一显示命令的第一同步信息。 控制电路被配置为基于第二同步信息和解码信号产生第一控制信号。 从第二显示控制器输出第二同步信息，并指示接收到第二显示命令。 视频输出逻辑电路被配置为发送存储在视频源中的视频数据的一部分和多个第一定时控制信号，用于基于第一控制信号将显示器上的视频数据的一部分显示在显示器上。

公开(公告)号：US08963798B2

公开(公告)日：2015-02-24

申请号：US13028491

申请日：2011-02-16

申请人： Dong Han Lee ,  Jong Ho Roh

发明人： Dong Han Lee ,  Jong Ho Roh

IPC分类号： G09G5/12 ,  G06F3/14

CPC分类号： G06F3/1438 ,  G06F3/1446 ,  G09G5/12

摘要： The display controller includes a decoder, a control circuit, and a video output logic circuit. The decoder is configured to decode a first display command and output a decoding signal and first synchronizing information indicating the first display command is received. The control circuit is configured to generate a first control signal based on second synchronizing information and the decoding signal. The second synchronizing information is output from a second display controller and indicates a second display command is received. The video output logic circuit is configured to send a part of video data stored in a video source and a plurality of first timing control signals for displaying the part of the video data on a display to the display based on the first control signal.

摘要翻译： 显示控制器包括解码器，控制电路和视频输出逻辑电路。 解码器被配置为对第一显示命令进行解码并输出解码信号，并且接收到表示第一显示命令的第一同步信息。 控制电路被配置为基于第二同步信息和解码信号产生第一控制信号。 从第二显示控制器输出第二同步信息，并指示接收到第二显示命令。 视频输出逻辑电路被配置为发送存储在视频源中的视频数据的一部分和多个第一定时控制信号，用于基于第一控制信号将显示器上的视频数据的一部分显示在显示器上。

公开(公告)号：US20120242707A1

公开(公告)日：2012-09-27

申请号：US13426796

申请日：2012-03-22

申请人： Min-Woo Song ,  Jong Ho Roh ,  Byoung Jin Ahn ,  Ho June Leu

发明人： Min-Woo Song ,  Jong Ho Roh ,  Byoung Jin Ahn ,  Ho June Leu

IPC分类号： G09G5/00 ,  G06K9/40 ,  G06K9/32

CPC分类号： G09G5/373 ,  G09G5/026 ,  G09G2340/0407

摘要： A scaler is provided and includes filters each receiving input pixel data and scaling the input pixel data using a scaling factor to generate a scaled pixel value, and a plurality of mixers, less than the plurality of filters. A first mixer performs a first blending operation on a first scaled pixel value and a second scaled pixel value provided by different filters. A second mixer performs a second blending operation on the blended result of the first mixer and a third scaled pixel value provided by anther filter.

摘要翻译： 提供了一种缩放器，并且包括各自接收输入像素数据并使用缩放因子缩放输入像素数据以生成缩放像素值的滤波器以及小于多个滤波器的多个混频器的滤波器。 第一混频器对由不同滤波器提供的第一缩放像素值和第二缩放像素值执行第一混合操作。 第二混频器对第一混频器的混合结果和由另一滤波器提供的第三缩放像素值执行第二混合操作。

公开(公告)号：US09066078B2

公开(公告)日：2015-06-23

申请号：US13617339

申请日：2012-09-14

申请人： Sung Chul Yoon ,  Jong Ho Roh

发明人： Sung Chul Yoon ,  Jong Ho Roh

IPC分类号： H04N13/00

CPC分类号： H04N13/139 ,  H04N2213/007

摘要： A display controller includes a merger and an alpha blender. The merger is configured to mix a first left frame including first left pixel data and a first right frame including first right pixel data based on a three-dimensional (3D) display format, and further configured and to output a first mixed frame and a second mixed frame. The alpha blender is configured to blend the first mixed frame and the second mixed frame to produce a first blended frame.

摘要翻译： 显示控制器包括合并器和α混合器。 合并被配置为基于三维（3D）显示格式混合包括第一左像素数据的第一左帧和包括第一右像素数据的第一右帧，并进一步配置并输出第一混合帧和第二混合帧 混合框架 α混合器配置成混合第一混合框架和第二混合框架以产生第一混合框架。

公开(公告)号：US08786637B2

公开(公告)日：2014-07-22

申请号：US13426796

申请日：2012-03-22

申请人： Min-Woo Song ,  Jong Ho Roh ,  Byoung Jin Ahn ,  Ho June Leu

发明人： Min-Woo Song ,  Jong Ho Roh ,  Byoung Jin Ahn ,  Ho June Leu

IPC分类号： G06T5/00

CPC分类号： G09G5/373 ,  G09G5/026 ,  G09G2340/0407

摘要： A scaler is provided and includes filters each receiving input pixel data and scaling the input pixel data using a scaling factor to generate a scaled pixel value, and a plurality of mixers, less than the plurality of filters. A first mixer performs a first blending operation on a first scaled pixel value and a second scaled pixel value provided by different filters. A second mixer performs a second blending operation on the blended result of the first mixer and a third scaled pixel value provided by anther filter.

摘要翻译： 提供了一种缩放器，并且包括各自接收输入像素数据并使用缩放因子缩放输入像素数据以生成缩放像素值的滤波器以及小于多个滤波器的多个混频器的滤波器。 第一混频器对由不同滤波器提供的第一缩放像素值和第二缩放像素值执行第一混合操作。 第二混频器对第一混频器的混合结果和由另一滤波器提供的第三缩放像素值执行第二混合操作。

公开(公告)号：US08713233B2

公开(公告)日：2014-04-29

申请号：US13050405

申请日：2011-03-17

申请人： Joon-Woo Cho ,  Jong Ho Roh ,  Jae Geun Yun ,  Sung-Min Hong

发明人： Joon-Woo Cho ,  Jong Ho Roh ,  Jae Geun Yun ,  Sung-Min Hong

IPC分类号： G06F13/00

CPC分类号： G06F13/368 ,  G06F12/0607 ,  G06F13/4022

摘要： Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.

摘要翻译： 提供互连，具有互连的总线系统和总线系统操作方法。 总线系统包括主机，主机的从机访问和互连。 响应于由主机提供的主地址中标识的选择位，互连将主机与从机连接。

公开(公告)号：US20110102465A1

公开(公告)日：2011-05-05

申请号：US12908465

申请日：2010-10-20

申请人： Sung Jin Cho ,  Jong Ho Roh

发明人： Sung Jin Cho ,  Jong Ho Roh

IPC分类号： G09G5/00

CPC分类号： G06T1/60

摘要： An image processor includes a rotation block and a scaler which share a line buffer block with each other. The image processor receives rearranged pixel data from a memory unit based on rotation information for generating a rotated image and performs scaling on the rearranged pixel data.

摘要翻译： 图像处理器包括彼此共享行缓冲块的旋转块和缩放器。 图像处理器基于用于生成旋转图像的旋转信息从存储器单元接收重新排列的像素数据，并对重新排列的像素数据执行缩放。

公开(公告)号：US10957018B2

公开(公告)日：2021-03-23

申请号：US14809149

申请日：2015-07-24

申请人： Eun Ji Kang ,  Hoon Mo Yang ,  Jong Ho Roh

发明人： Eun Ji Kang ,  Hoon Mo Yang ,  Jong Ho Roh

IPC分类号： G06F1/16 ,  G06T3/60 ,  G06F3/01 ,  G09G5/00 ,  G06F3/03

摘要： A portable electronic device comprises a double-sided display including a first display side and a second display side formed on a side opposite the first display side; a direct memory access (DMA) controller configured to read first image data from a memory; at least one sensor configured to detect at least one of a position change of the double-sided display and a movement of a user's pupil and to output a detection signal; a status signal generator configured to interpret the detection signal output and to output a status signal; a transmission order determiner configured to receive the first image data from the DMA controller, to determine a transmission order of the first image data based on the status signal, and to output second image data corresponding to the determined transmission order; and a display driver integrated circuit (IC) configured to transmit the second image data to the display.

公开(公告)号：US08836612B2

公开(公告)日：2014-09-16

申请号：US12783875

申请日：2010-05-20

申请人： Jong Ho Roh

发明人： Jong Ho Roh

IPC分类号： G09G3/36 ,  G06F3/14 ,  G09G5/18

CPC分类号： G06F3/1431 ,  G06F3/1446 ,  G09G3/3611 ,  G09G5/18

摘要： A device includes a plurality of display modules configured to commonly receive a stream of video data from a controller and a video control masking unit. Each display module includes a display device. The video control masking unit receives one or more control signals that indicate how the video data is to be displayed by the display modules, and further receives at least one of: a clock signal for clocking the stream of video data that is provided in common to the plurality of display modules, and a data enable signal for enabling the display modules to process the video data; and in response thereto the video control masking unit masks at least one of the clock signal and the data enable signal to generate a plurality of masked signals each corresponding to one of the display modules, and provides each of the masked signals to the corresponding display module.

摘要翻译： 一种设备包括多个显示模块，其被配置为从控制器和视频控制屏蔽单元共同接收视频数据流。 每个显示模块包括显示装置。 视频控制屏蔽单元接收一个或多个指示视频数据将如何由显示模块显示的控制信号，并且还接收以下中的至少一个：时钟信号，用于将通常提供的视频数据流计时 多个显示模块和用于使显示模块能够处理视频数据的数据使能信号; 并且响应于此，视频控制屏蔽单元屏蔽时钟信号和数据使能信号中的至少一个以产生每个对应于一个显示模块的多个屏蔽信号，并将每个屏蔽信号提供给相应的显示模块 。

公开(公告)号：US20120075262A1

公开(公告)日：2012-03-29

申请号：US13206704

申请日：2011-08-10

申请人： Kyoung Man Kim ,  Jong Ho Roh ,  Jae Sop Kong

发明人： Kyoung Man Kim ,  Jong Ho Roh ,  Jae Sop Kong

IPC分类号： G09G5/00

CPC分类号： G09G5/363

摘要： An under-run compensation circuit is provided. The under-run compensation circuit is configured to receive a clock signal, data, and an under-run detection signal that indicates whether or not an under-run is occurring. The under-run compensation circuit is further configured to output the clock signal and the data when receiving the under-run detection signal that indicates that an under-run is not occurring. The under-run compensation circuit is additionally configured to output the clock signal and dummy data when receiving the under- run detection signal that indicates that an under-run is occurring.

摘要翻译： 提供欠运行补偿电路。 欠运行补偿电路被配置为接收指示是否发生欠运行的时钟信号，数据和欠运行检测信号。 欠运行补偿电路还被配置为当接收到指示未发生欠运行的欠运行检测信号时输出时钟信号和数据。 欠运行补偿电路还被配置为当接收到指示发生欠运行的欠运行检测信号时输出时钟信号和伪数据。