公开(公告)号：US06399488B2

公开(公告)日：2002-06-04

申请号：US09879555

申请日：2001-06-12

申请人： Dong Suk Shin ,  Woo Seok Cheong ,  Bong Soo Kim

发明人： Dong Suk Shin ,  Woo Seok Cheong ,  Bong Soo Kim

IPC分类号： H01L2144

CPC分类号： H01L21/28525 ,  H01L21/28562

摘要： A method of manufacturing a contact plug in a semiconductor device is disclosed. In-situ thermal doping of an impurity such as phosphorous (P) during the process by which polysilicon for a contact plug is formed by selective growth method and after in-situ doping after the growth process is employed in order to increase the concentration of the impurity in the contact plug. As a result, the disclosed method can reduce the interfacial resistance at the plug to improve the electrical characteristics of a device of more than 1 G bits.

摘要翻译： 公开了一种在半导体器件中制造接触插塞的方法。 在用于接触塞的多晶硅通过选择性生长方法和在生长过程之后的原位掺杂之后的过程中，诸如磷（P）的杂质的原位热掺杂以增加其浓度 接触塞中的杂质。 结果，所公开的方法可以降低插头处的界面电阻以改善超过1G位的器件的电气特性。

公开(公告)号：US08742806B2

公开(公告)日：2014-06-03

申请号：US13442426

申请日：2012-04-09

申请人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

发明人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

IPC分类号： H03L7/06 ,  H03L7/081

CPC分类号： H03L7/0812

摘要： A method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a Delay Locked Loop (DLL) circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal.

摘要翻译： 一种控制功率控制电路的方法包括：当延迟锁定环路（DLL）电路的延迟锁定操作完成时，使能电源切断信号，在预定时间内禁用电源切断信号，并检测参考时钟 以及反馈时钟，基于检测结果来重新确定是否启用电源切断信号。

公开(公告)号：US08390353B2

公开(公告)日：2013-03-05

申请号：US13332964

申请日：2011-12-21

申请人： Dong Suk Shin ,  Kwang Jin Na

发明人： Dong Suk Shin ,  Kwang Jin Na

IPC分类号： H03K3/017

CPC分类号： H03K5/04

摘要： A duty cycle correction circuit includes a duty correction block configured to generate a first pre-corrected signal and a second pre-corrected signal in response to a duty code and an input signal; a duty-corrected signal generation block configured to generate a duty-corrected signal in response to a first select signal, a second select signal, the first pre-corrected signal and the second pre-corrected signal; and a control block configured to generate the duty code, the first select signal and the second select signal in response to the duty-corrected signal and the input signal.

摘要翻译： 占空比校正电路包括占空比校正块，其被配置为响应于占空比代码和输入信号产生第一预校正信号和第二预校正信号; 配置为响应于第一选择信号，第二选择信号，第一预校正信号和第二预校正信号产生占空比校正信号的占空比校正信号产生块; 以及控制块，被配置为响应于占空比校正信号和输入信号而产生占空比代码，第一选择信号和第二选择信号。

公开(公告)号：US20100213920A1

公开(公告)日：2010-08-26

申请号：US12770702

申请日：2010-04-29

申请人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

发明人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

IPC分类号： G05B24/02

CPC分类号： H03L7/0812

摘要： A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal.

摘要翻译： 功率控制电路包括：检查单元，接收参考时钟并产生用于循环地激活DLL电路的反馈回路的检查信号;相位检测单元，其检测参考时钟和反馈时钟之间的相位差，并产生 相位差检测信号，以及响应于锁定完成信号，检查信号和相位差检测信号产生电力切断信号的信号组合单元。

公开(公告)号：US20090273382A1

公开(公告)日：2009-11-05

申请号：US12500007

申请日：2009-07-09

申请人： Dong Suk Shin ,  Hyun Woo Lee ,  Won Joo Yun

发明人： Dong Suk Shin ,  Hyun Woo Lee ,  Won Joo Yun

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K2005/00058 ,  H03K2005/00221

摘要： A circuit configured to correct a duty cycle includes a clock dividing unit configured to delay an input clock signal by a specified delay amount and to generate a plurality of delayed clock signals, a clock selection unit configured to output any one among the plurality of delayed clock signals as a selected delayed clock signal in response to duty ratio information of the input clock signal, an edge control unit configured to generate a falling clock signal by controlling a falling edge of the selected delayed clock signal and to generate a rising clock signal by controlling a falling edge of the input clock signal based on information regarding a difference between lengths of a high duration and a low duration of the input clock signal, and a phase mixing unit for mixing phases of the falling clock signal and the rising clock signal and generating an output clock signal.

摘要翻译： 配置为校正占空比的电路包括时钟分频单元，被配置为将输入时钟信号延迟指定的延迟量并产生多个延迟时钟信号;时钟选择单元，被配置为输出多个延迟时钟 信号作为响应于输入时钟信号的占空比信息的选择的延迟时钟信号;边缘控制单元，被配置为通过控制所选择的延迟时钟信号的下降沿来产生下降时钟信号，并通过控制产生上升时钟信号 基于关于输入时钟信号的高持续时间和低持续时间之间的差的信息的输入时钟信号的下降沿，以及用于混合下降时钟信号和上升时钟信号的相位的相位混合单元，并产生 输出时钟信号。

公开(公告)号：US20080252350A1

公开(公告)日：2008-10-16

申请号：US11961931

申请日：2007-12-20

申请人： Dong Suk Shin ,  Hyun Woo Lee ,  Won Joo Yun

发明人： Dong Suk Shin ,  Hyun Woo Lee ,  Won Joo Yun

IPC分类号： H03K5/04

CPC分类号： H03K5/1565 ,  H03K2005/00058 ,  H03K2005/00221

摘要： A circuit for correcting a duty cycle includes a duty ratio digital conversion block configured to output duty ratio information of an input clock signal as plural-bit digital signals, a duty ratio information analyzing block configured to analyze the duty ratio information of the input clock signal, generate edge control signals, and select any one of a plurality of delayed clock signals, and a duty ratio control block configured to control duty ratios of a selected delayed clock signal and the input clock signal in response to the edge control signals.

摘要翻译： 用于校正占空比的电路包括占空比数字转换块，被配置为输出作为多位数字信号的输入时钟信号的占空比信息;占空比信息分析块，被配置为分析输入时钟信号的占空比信息 产生边沿控制信号，并选择多个延迟时钟信号中的任一个，以及占空比控制块，被配置为响应于边沿控制信号来控制所选择的延迟时钟信号和输入时钟信号的占空比。

公开(公告)号：US20080252349A1

公开(公告)日：2008-10-16

申请号：US11959368

申请日：2007-12-18

申请人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

发明人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

IPC分类号： H03K5/04

CPC分类号： H03K5/1565 ,  H03K2005/00058 ,  H03K2005/00208

摘要： A duty cycle correcting circuit includes a duty ratio control signal generating block that detects a duty ratio of input clock signals and generates a duty ratio control signal comprising a plurality of bits, a power supply block that supplies a voltage to output nodes, and a signal processing block that controls voltage levels of the output nodes to correspond to voltage levels of the input clock signals in response to the plurality of bits of duty ratio control signals.

摘要翻译： 占空比校正电路包括占空比控制信号产生块，其检测输入时钟信号的占空比，并产生包括多个位的占空比控制信号，向输出节点提供电压的电源块和信号 处理块，其响应于所述多个位占空比控制信号来控制所述输出节点的电压电平以对应于所述输入时钟信号的电压电平。

公开(公告)号：US06908853B2

公开(公告)日：2005-06-21

申请号：US10034243

申请日：2001-12-28

申请人： Dong Suk Shin

发明人： Dong Suk Shin

IPC分类号： H01L21/30 ,  H01L21/285 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/28525 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76879

摘要： A method of fabricating a semiconductor device having the steps of forming an insulating layer on a silicon substrate; forming a contact hole in the insulating layer so that a portion of the silicon substrate is exposed in the contact hole; performing an interface treatment process to the exposed portion of the silicon substrate, wherein the interface treatment process includes at least a dry cleaning and a hydrogen heat treatment; and forming a selective silicon plug including single crystalline and polycrystalline silicon structures on the exposed portion of the silicon substrate.

摘要翻译： 一种制造半导体器件的方法，具有在硅衬底上形成绝缘层的步骤; 在所述绝缘层中形成接触孔，使得所述硅基板的一部分露出在所述接触孔中; 对所述硅衬底的暴露部分进行界面处理工艺，其中所述界面处理工艺至少包括干法清洗和氢热处理; 以及在硅衬底的暴露部分上形成包括单晶和多晶硅结构的选择性硅插头。

公开(公告)号：US08330512B2

公开(公告)日：2012-12-11

申请号：US12843568

申请日：2010-07-26

申请人： Ki Han Kim ,  Dong Suk Shin

发明人： Ki Han Kim ,  Dong Suk Shin

IPC分类号： H03L7/06

CPC分类号： H03H11/265 ,  H03L7/0816

摘要： A clock generation circuit of a semiconductor apparatus includes a first phase detection block configured to compare initial phases of a reference clock signal and an output clock signal in response to an operation start signal, and output an initial phase difference detection signal corresponding to a comparison result; a second phase detection block configured to compare phases of the reference clock signal and the output clock signal, and output a phase detection signal corresponding to a comparison result; a variable unit delay block determined in a control range of the delay amount thereof in response to the initial phase difference detection signal, and configured to delay the reference clock signal by a delay amount corresponding to a voltage level of a control voltage and output the output clock signal; and a delay control block configured to generate the control voltage which has the voltage level corresponding to the phase detection signal.

摘要翻译： 半导体装置的时钟生成电路包括第一相位检测块，其被配置为响应于操作开始信号来比较参考时钟信号和输出时钟信号的初始相位，并且输出与比较结果相对应的初始相位差检测信号 ; 第二相位检测块，被配置为比较参考时钟信号和输出时钟信号的相位，并输出与比较结果对应的相位检测信号; 响应于初始相位差检测信号在其延迟量的控制范围内确定的可变单位延迟块，并且被配置为将参考时钟信号延迟与控制电压的电压电平相对应的延迟量，并输出输出 时钟信号; 以及延迟控制块，被配置为产生具有与相位检测信号相对应的电压电平的控制电压。

公开(公告)号：US08278985B2

公开(公告)日：2012-10-02

申请号：US12983177

申请日：2010-12-31

申请人： Dong Suk Shin

发明人： Dong Suk Shin

IPC分类号： H03L7/06

CPC分类号： G11C8/18 ,  G11C8/04 ,  H03L7/0812

摘要： A synchronization circuit includes a first loop circuit configured to set an initial delay time by using first initial delay information and generate a first delay signal by changing a delay time of a first input signal, a second loop circuit configured to set the initial delay time by using second initial delay information and generate a second delay signal by changing a delay time of a second input signal, a duty cycle correction unit configured to correct a duty cycle of the first delay signal by using the second delay signal, and an initial delay monitoring circuit configured to generate the first initial delay information and the second initial delay information in response to an internal delay signal of the first loop circuit and the first input signal.

摘要翻译： 同步电路包括第一环路电路，其被配置为通过使用第一初始延迟信息来设置初始延迟时间，并且通过改变第一输入信号的延迟时间来产生第一延迟信号，第二环路电路被配置为将初始延迟时间设置为 使用第二初始延迟信息并通过改变第二输入信号的延迟时间来产生第二延迟信号;占空比校正单元，被配置为通过使用第二延迟信号来校正第一延迟信号的占空比，以及初始延迟监视 电路，被配置为响应于第一环路电路和第一输入信号的内部延迟信号产生第一初始延迟信息和第二初始延迟信息。