公开(公告)号：US08154326B2

公开(公告)日：2012-04-10

申请号：US12770702

申请日：2010-04-29

申请人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

发明人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal.

摘要翻译： 功率控制电路包括：检查单元，接收参考时钟并产生用于循环地激活DLL电路的反馈回路的检查信号;相位检测单元，其检测参考时钟和反馈时钟之间的相位差，并产生 相位差检测信号，以及响应于锁定完成信号，检查信号和相位差检测信号产生电力切断信号的信号组合单元。

公开(公告)号：US07750703B2

公开(公告)日：2010-07-06

申请号：US11959368

申请日：2007-12-18

申请人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

发明人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

IPC分类号： H03K5/04

CPC分类号： H03K5/1565 ,  H03K2005/00058 ,  H03K2005/00208

摘要： A duty cycle correcting circuit includes a duty ratio control signal generating block that detects a duty ratio of input clock signals and generates a duty ratio control signal comprising a plurality of bits, a power supply block that supplies a voltage to output nodes, and a signal processing block that controls voltage levels of the output nodes to correspond to voltage levels of the input clock signals in response to the plurality of bits of duty ratio control signals.

摘要翻译： 占空比校正电路包括占空比控制信号产生块，其检测输入时钟信号的占空比，并产生包括多个位的占空比控制信号，向输出节点提供电压的电源块和信号 处理块，其响应于所述多个位占空比控制信号来控制所述输出节点的电压电平以对应于所述输入时钟信号的电压电平。

公开(公告)号：US20090003101A1

公开(公告)日：2009-01-01

申请号：US12013866

申请日：2008-01-14

申请人： Won-Joo Yun ,  Hyun Woo Lee ,  Dong-Suk Shin

发明人： Won-Joo Yun ,  Hyun Woo Lee ,  Dong-Suk Shin

IPC分类号： G11C29/00

CPC分类号： G11C29/46 ,  G11C29/14 ,  G11C2029/0407 ,  Y10T307/747 ,  Y10T307/826 ,  Y10T307/858 ,  Y10T307/977

摘要： An apparatus for setting a test mode in a semiconductor integrated circuit includes a test mode control block that generates a coding control signal according to whether or not a control fuse is cut, and a test mode coding block that sets default values of a multi-bit test code in response to the coding control signal.

摘要翻译： 一种用于在半导体集成电路中设置测试模式的装置包括：测试模式控制块，其根据是否切断控制熔丝产生编码控制信号;以及测试模式编码块，其设置多位的默认值 响应于编码控制信号的测试码。

公开(公告)号：US20080174350A1

公开(公告)日：2008-07-24

申请号：US11826401

申请日：2007-07-16

申请人： Dong Suk Shin ,  Hyun Woo Lee ,  Won Joo Yun

发明人： Dong Suk Shin ,  Hyun Woo Lee ,  Won Joo Yun

IPC分类号： H03L7/08 ,  H03K5/14 ,  H03L7/07

CPC分类号： H03K5/133 ,  H03K5/1565 ,  H03K2005/00052 ,  H03K2005/00065 ,  H03L7/0814 ,  H03L7/087

摘要： A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction control unit generates a correction control signal in response to the duty ratio detection signal. A duty ratio correction unit corrects a duty ratio of an internal. clock in response to the correction control signal, thereby outputting a reference clock.

摘要翻译： DLL电路包括占空比检测单元，其检测上升时钟的占空比和下降时钟的占空比，从而输出占空比检测信号。 校正控制单元响应于占空比检测信号产生校正控制信号。 占空比校正单元校正内部的占空比。 响应于校正控制信号，从而输出参考时钟。

公开(公告)号：US20100134155A1

公开(公告)日：2010-06-03

申请号：US12698606

申请日：2010-02-02

申请人： Hyun Woo Lee ,  Won Joo Yun ,  Dong Suk Shin

发明人： Hyun Woo Lee ,  Won Joo Yun ,  Dong Suk Shin

IPC分类号： H03L7/00 ,  H03L7/06

CPC分类号： G11C7/02 ,  G11C5/143 ,  G11C5/144 ,  G11C7/22 ,  G11C7/222

摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.

摘要翻译： 断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率 下降模式信号和内部掉电信号。

公开(公告)号：US07719333B2

公开(公告)日：2010-05-18

申请号：US11964802

申请日：2007-12-27

申请人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

发明人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal.

摘要翻译： 功率控制电路包括：检查单元，接收参考时钟并产生用于循环地激活DLL电路的反馈回路的检查信号;相位检测单元，其检测参考时钟和反馈时钟之间的相位差，并产生 相位差检测信号，以及响应于锁定完成信号，检查信号和相位差检测信号产生电力切断信号的信号组合单元。

公开(公告)号：US07782106B2

公开(公告)日：2010-08-24

申请号：US12500007

申请日：2009-07-09

申请人： Dong Suk Shin ,  Hyun Woo Lee ,  Won Joo Yun

发明人： Dong Suk Shin ,  Hyun Woo Lee ,  Won Joo Yun

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K2005/00058 ,  H03K2005/00221

摘要： A circuit configured to correct a duty cycle includes a clock dividing unit configured to delay an input clock signal by a specified delay amount and to generate a plurality of delayed clock signals, a clock selection unit configured to output any one among the plurality of delayed clock signals as a selected delayed clock signal in response to duty ratio information of the input clock signal, an edge control unit configured to generate a falling clock signal by controlling a falling edge of the selected delayed clock signal and to generate a rising clock signal by controlling a falling edge of the input clock signal based on information regarding a difference between lengths of a high duration and a low duration of the input clock signal, and a phase mixing unit for mixing phases of the falling clock signal and the rising clock signal and generating an output clock signal.

摘要翻译： 配置为校正占空比的电路包括时钟分频单元，被配置为将输入时钟信号延迟指定的延迟量并产生多个延迟时钟信号;时钟选择单元，被配置为输出多个延迟时钟 信号作为响应于输入时钟信号的占空比信息的选择的延迟时钟信号;边缘控制单元，被配置为通过控制所选择的延迟时钟信号的下降沿来产生下降时钟信号，并通过控制产生上升时钟信号 基于关于输入时钟信号的高持续时间和低持续时间之间的差的信息的输入时钟信号的下降沿，以及用于混合下降时钟信号和上升时钟信号的相位的相位混合单元，并产生 输出时钟信号。

公开(公告)号：US07576581B2

公开(公告)日：2009-08-18

申请号：US11961931

申请日：2007-12-20

申请人： Dong Suk Shin ,  Hyun Woo Lee ,  Won Joo Yun

发明人： Dong Suk Shin ,  Hyun Woo Lee ,  Won Joo Yun

IPC分类号： H03K5/04

CPC分类号： H03K5/1565 ,  H03K2005/00058 ,  H03K2005/00221

摘要： A circuit for correcting a duty cycle includes a duty ratio digital conversion block configured to output duty ratio information of an input clock signal as plural-bit digital signals, a duty ratio information analyzing block configured to analyze the duty ratio information of the input clock signal, generate edge control signals, and select any one of a plurality of delayed clock signals, and a duty ratio control block configured to control duty ratios of a selected delayed clock signal and the input clock signal in response to the edge control signals.

摘要翻译： 用于校正占空比的电路包括占空比数字转换块，被配置为输出作为多位数字信号的输入时钟信号的占空比信息;占空比信息分析块，被配置为分析输入时钟信号的占空比信息 产生边沿控制信号，并选择多个延迟时钟信号中的任一个，以及占空比控制块，被配置为响应于边沿控制信号来控制所选择的延迟时钟信号和输入时钟信号的占空比。

公开(公告)号：US20090002039A1

公开(公告)日：2009-01-01

申请号：US11964802

申请日：2007-12-27

申请人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

发明人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal.

摘要翻译： 功率控制电路包括：检查单元，接收参考时钟并产生用于循环地激活DLL电路的反馈回路的检查信号;相位检测单元，其检测参考时钟和反馈时钟之间的相位差，并产生 相位差检测信号，以及响应于锁定完成信号，检查信号和相位差检测信号产生电力切断信号的信号组合单元。

公开(公告)号：US08742806B2

公开(公告)日：2014-06-03

申请号：US13442426

申请日：2012-04-09

申请人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

发明人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

IPC分类号： H03L7/06 ,  H03L7/081

CPC分类号： H03L7/0812

摘要： A method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a Delay Locked Loop (DLL) circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal.

摘要翻译： 一种控制功率控制电路的方法包括：当延迟锁定环路（DLL）电路的延迟锁定操作完成时，使能电源切断信号，在预定时间内禁用电源切断信号，并检测参考时钟 以及反馈时钟，基于检测结果来重新确定是否启用电源切断信号。