中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.014 seconds)

    FLASH MEMORY DEVICE HAVING MULTI-LEVEL CELL AND READING AND PROGRAMMING METHOD THEREOF
    1.
    发明申请
    FLASH MEMORY DEVICE HAVING MULTI-LEVEL CELL AND READING AND PROGRAMMING METHOD THEREOF 有权
    具有多级单元的闪存存储器件及其读取和编程方法

    公开(公告)号：US20080151632A1

    公开(公告)日：2008-06-26

    申请号：US12035357

    申请日：2008-02-21

    Applicant: Dong-Hwan KIM ,  Yeong-Taek LEE

    Inventor： Dong-Hwan KIM ,  Yeong-Taek LEE

    IPC: G11C16/06

    CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5642

    Abstract: There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and first to third latch circuits each of which performs different function from each other. The reading and programming methods are performed by LSB and MSB reading and programming operations. A reading method in the memory device is achieved by reading an LSB two times and by reading an MSB one time. A programming method is achieved by programming an LSB one time and programming an MSB one time. Data having multi-levels can be programmed into memory cells by two times programming operations.

    Abstract translation: 提供了一种具有多电平单元的闪存器件及其读取和编程方法。 具有多电平单元的闪速存储器件包括存储单元阵列，用于对位线进行预充电的单元，用于向位线提供电压的位线电压供应电路，以及每个都执行与位线不同的功能的第一至第三锁存电路 彼此。 读取和编程方法由LSB和MSB读取和编程操作执行。 通过读取LSB两次并通过读取MSB一次来实现存储器件中的读取方法。 通过编程LSB一次并编程MSB一次来实现编程方法。 具有多级数据的数据可以通过两次编程操作被编程到存储器单元中。

    FLASH MEMORY DEVICE HAVING MULTI-LEVEL CELL AND READING AND PROGRAMMING METHOD THEREOF
    2.
    发明申请
    FLASH MEMORY DEVICE HAVING MULTI-LEVEL CELL AND READING AND PROGRAMMING METHOD THEREOF 有权
    具有多级单元的闪存存储器件及其读取和编程方法

    公开(公告)号：US20090122606A1

    公开(公告)日：2009-05-14

    申请号：US12348168

    申请日：2009-01-02

    Applicant: Dong-Hwan KIM ,  Yeong-Taek LEE

    Inventor： Dong-Hwan KIM ,  Yeong-Taek LEE

    IPC: G11C16/06 ,  G11C16/00

    CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5642

    Abstract: There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and first to third latch circuits each of which performs different function from each other. The reading and programming methods are performed by LSB and MSB reading and programming operations. A reading method in the memory device is achieved by reading an LSB two times and by reading an MSB one time. A programming method is achieved by programming an LSB one time and programming an MSB one time. Data having multi-levels can be programmed into memory cells by two times programming operations.

    Abstract translation: 提供了一种具有多电平单元的闪存器件及其读取和编程方法。 具有多电平单元的闪速存储器件包括存储单元阵列，用于对位线进行预充电的单元，用于向位线提供电压的位线电压供应电路，以及每个都执行与位线不同的功能的第一至第三锁存电路 彼此。 读取和编程方法由LSB和MSB读取和编程操作执行。 通过读取LSB两次并通过读取MSB一次来实现存储器件中的读取方法。 通过编程LSB一次并编程MSB一次来实现编程方法。 具有多级数据的数据可以通过两次编程操作被编程到存储器单元中。

    NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD WITH IMPROVED PASS VOLTAGE WINDOW
    3.
    发明申请
    NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD WITH IMPROVED PASS VOLTAGE WINDOW 有权
    非易失性存储器件和具有改进的电压窗口的程序方法

    公开(公告)号：US20100067305A1

    公开(公告)日：2010-03-18

    申请号：US12509612

    申请日：2009-07-27

    Applicant: Ki-Tae PARK ,  Yeong-Taek LEE ,  Soon-Wook HWANG ,  Young-Wook JEONG

    Inventor： Ki-Tae PARK ,  Yeong-Taek LEE ,  Soon-Wook HWANG ,  Young-Wook JEONG

    IPC: G11C16/04 ,  G11C5/14

    CPC classification number: G11C16/12 ,  G11C16/0483

    Abstract: A flash memory and programming method are disclosed. The flash memory includes a memory cell array having memory cells arranged in a plurality of word lines including a selected word line and a plurality of non-selected word lines and a plurality of bit lines, a high voltage generator generating a program voltage applied to the selected word line, and a pass voltage applied to at least one of the non-selected word lines adjacent to the selected word line, and control logic controlling the generation of the program voltage, such that the program voltage is incrementally increased during a program operation, and generation of the pass voltage, such that the program voltage is incrementally increased.

    Abstract translation: 公开了闪存和编程方法。 闪速存储器包括存储单元阵列，该存储单元阵列具有布置在包括所选择的字线和多个未选择的字线和多个位线的多个字线中的存储器单元，高电压发生器产生施加到该字线的编程电压 所选择的字线和施加到与所选字线相邻的未选择的字线中的至少一个的通过电压，以及控制逻辑，以控制编程电压的产生，使得编程电压在编程操作期间递增地增加 ，并产生通过电压，使得编程电压递增地增加。

    NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING
    4.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING 有权
    非易失性存储器件和操作方法

    公开(公告)号：US20080316818A1

    公开(公告)日：2008-12-25

    申请号：US12141737

    申请日：2008-06-18

    Applicant: Ki-Tae PARK ,  Doo-Gon KIM ,  Yeong-Taek LEE

    Inventor： Ki-Tae PARK ,  Doo-Gon KIM ,  Yeong-Taek LEE

    IPC: G11C16/06

    CPC classification number: G11C16/3418

    Abstract: A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and providing a read voltage to the gate of the selected memory cell and providing a second pass voltage to the gate of the non-selected memory cell during a read operation. The second pass voltage is greater than the first pass voltage.

    Abstract translation: 一种非易失性存储器件和操作方法，包括向多个存储器单元内的所选存储单元的栅极提供验证电压，并且在程序验证期间向存储器单元内的未选择存储单元的栅极提供第一通过电压 操作; 以及向所选择的存储单元的栅极提供读取电压，并且在读取操作期间向未选择的存储单元的栅极提供第二通过电压。 第二通过电压大于第一通过电压。

    SILICON-CONTROLLED RECTIFIER FOR ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS AND STRUCTURE THEREOF
    6.
    发明申请
    SILICON-CONTROLLED RECTIFIER FOR ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS AND STRUCTURE THEREOF 有权
    用于静电放电保护电路的硅控整流器及其结构

    公开(公告)号：US20070034896A1

    公开(公告)日：2007-02-15

    申请号：US11461681

    申请日：2006-08-01

    Applicant: Ki-Whan SONG ,  Yeong-Taek LEE

    Inventor： Ki-Whan SONG ,  Yeong-Taek LEE

    IPC: H01L29/74

    CPC classification number: H01L27/0262

    Abstract: A Silicon-Controlled Rectifier (SCR) for Electrostatic Discharge (ESD) protection includes an isolation device. The isolation device isolates a main ground voltage line, connected to a first cathode, from a peripheral ground voltage line, connected to a second cathode. As result, even when noise occurs in the peripheral ground voltage line during the operation of an integrated circuit, the main ground voltage line maintains a stable voltage level.

    Abstract translation: 用于静电放电（ESD）保护的硅控整流器（SCR）包括隔离装置。 隔离装置将连接到第一阴极的主接地电压线与连接到第二阴极的外围接地电压线隔离。 因此，即使在集成电路的动作中，外围接地电压线发生噪声时，主接地电压线保持稳定的电压电平。

    THREE-DIMENSIONAL MEMORY DEVICE
    8.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE 审中-公开
    三维存储器件

    公开(公告)号：US20090168482A1

    公开(公告)日：2009-07-02

    申请号：US12343630

    申请日：2008-12-24

    Applicant: Ki-Tae PARK ,  Yeong-Taek LEE ,  Doo-Gon KIM

    Inventor： Ki-Tae PARK ,  Yeong-Taek LEE ,  Doo-Gon KIM

    IPC: G11C17/08 ,  G11C5/02

    CPC classification number: G11C16/0483 ,  G11C5/02 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    Abstract: A three-dimensional memory device includes a base layer having a memory array and peripheral circuits formed on a bulk silicon substrate, and N circuit layers each having a memory array formed on a silicon-on-insulator (SOI) substrate. The N circuit layers are vertically stacked one on top of the other on the base layer and the uppermost Nth circuit layer additionally includes passive elements

    Abstract translation: 三维存储器件包括具有存储器阵列的基底层和形成在体硅衬底上的外围电路，以及每个具有形成在绝缘体上硅（SOI））衬底上的存储器阵列的N个电路层。 N个电路层在基极层上垂直堆叠在一起，而最上面的第N个电路层另外包括无源元件

    METHOD OF ERASING IN NON-VOLATILE MEMORY DEVICE
    9.
    发明申请
    METHOD OF ERASING IN NON-VOLATILE MEMORY DEVICE 有权
    非易失性存储器件中的擦除方法

    公开(公告)号：US20080304326A1

    公开(公告)日：2008-12-11

    申请号：US12136968

    申请日：2008-06-11

    Applicant: Doo-Gon KIM ,  Ki-Tae PARK ,  Yeong-Taek LEE

    Inventor： Doo-Gon KIM ,  Ki-Tae PARK ,  Yeong-Taek LEE

    IPC: G11C16/06

    CPC classification number: G11C16/14

    Abstract: An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage.

    Abstract translation: 一种在非易失性存储器件中进行后编程的擦除方法。 该方法包括后编程虚拟存储器单元; 验证所述伪存储单元的阈值电压是否大于或等于第一电压; 后编程正常记忆单元; 以及验证所述正常存储单元的阈值电压是否大于或等于第二电压。 第一电压与第二电压不同。

Patent Agency Ranking