公开(公告)号：US08823892B2

公开(公告)日：2014-09-02

申请号：US13155868

申请日：2011-06-08

Applicant: Dong-Gyu Kim ,  Hye-Seok Na ,  Mee-Hye Jung ,  Dong-Hyeon Ki ,  Se-Hyoung Cho

Inventor： Dong-Gyu Kim ,  Hye-Seok Na ,  Mee-Hye Jung ,  Dong-Hyeon Ki ,  Se-Hyoung Cho

IPC: G02F1/136 ,  G02F1/1343 ,  G02F1/141 ,  G02F1/1362 ,  G09G3/36 ,  G02F1/139

CPC classification number: G02F1/1393 ,  G02F1/134363 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/13624 ,  G02F1/136286 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2300/0452

Abstract: A liquid crystal display device includes a substrate, a gate line, first and second data lines, a first power line, first, second, third and fourth switching elements, and first, second, third and fourth pixel electrodes. The first switching element is connected to the gate line and the first data line. The second switching element is connected to the gate line and the first power line. The third switching element is connected to the gate line and the second data line. The fourth switching element is connected to the gate line and the first power line. The first to fourth pixel electrodes are connected to the first to fourth switching elements, respectively. Thus, a light leakage may be prevented and an aperture ratio of a display substrate may be enhanced.

Abstract translation: 液晶显示装置包括基板，栅极线，第一和第二数据线，第一电力线，第一，第二，第三和第四开关元件以及第一，第二，第三和第四像素电极。 第一开关元件连接到栅极线和第一数据线。 第二开关元件连接到栅极线和第一电力线。 第三开关元件连接到栅极线和第二数据线。 第四开关元件连接到栅极线和第一电力线。 第一至第四像素电极分别连接到第一至第四开关元件。 因此，可以防止漏光，并且可以提高显示基板的开口率。

公开(公告)号：US08610863B2

公开(公告)日：2013-12-17

申请号：US12019440

申请日：2008-01-24

Applicant: Ji-Hyun Kwon ,  Hyeok-Jin Lee ,  Byoung-Sun Na ,  Lujian Gang ,  Dong-Hyeon Ki ,  Hwa-Sung Woo

Inventor： Ji-Hyun Kwon ,  Hyeok-Jin Lee ,  Byoung-Sun Na ,  Lujian Gang ,  Dong-Hyeon Ki ,  Hwa-Sung Woo

IPC: G02F1/1343

CPC classification number: G02F1/136286 ,  G02F1/134309 ,  G02F2001/134318 ,  G02F2001/136218 ,  G02F2201/121 ,  G02F2201/122

Abstract: An LCD panel is provided for improving a contrast ratio by suppressing light leakage around gate lines of an assembly that is structured to support a liquid crystal alignment mode that enhanced side view visibility of the LCD image. The LCD panel includes a first base substrate, a plurality of gate lines and a plurality of data lines disposed on the first base substrate and crossing each other, a pixel electrode comprising a first oblique line and a second oblique line disposed on the first base substrate and inclined in a different direction from each other with respect to the gate lines, a second base substrate, a common electrode disposed on the second base substrate and alternately positioned with the pixel electrode, wherein a portion of the common electrode overlaps the gate line segment, and a liquid crystal layer disposed between the first and second base substrates.

Abstract translation: 提供一种LCD面板，用于通过抑制组件的栅极线周围的光泄漏来提高对比度，该组件被构造成支持提高LCD图像的侧视可见度的液晶对准模式。 LCD面板包括第一基底基板，多条栅极线和设置在第一基底基板上并彼此交叉的多条数据线，包括设置在第一基底基板上的第一斜线和第二斜线的像素电极 并且相对于栅极线彼此不同的方向倾斜，第二基底基板，设置在第二基底基板上并与像素电极交替定位的公共电极，其中，公共电极的一部分与栅极线段重叠 以及设置在第一和第二基底之间的液晶层。

公开(公告)号：US08228282B2

公开(公告)日：2012-07-24

申请号：US11928466

申请日：2007-10-30

Applicant: Byoung-Sun Na ,  Dong-Hyeon Ki ,  Min-Cheol Lee ,  Soon-Il Ahn

Inventor： Byoung-Sun Na ,  Dong-Hyeon Ki ,  Min-Cheol Lee ,  Soon-Il Ahn

IPC: G09G3/36

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2320/0219 ,  G09G2320/041

Abstract: In a gate driving circuit and a display apparatus having the gate driving circuit, a pull-up transistor of a present stage among plural stages, which are connected one after another to each other and sequentially output a gate signal, pulls up a present gate signal output through an output terminal to a gate-on voltage. A buffer transistor is connected to a control terminal of the pull-up transistor to receive a previous output signal from a previous stage and to turn on the pull-up transistor. The buffer transistor has a chargeability that is about two times or greater than the chargeability of the pull-up transistor. Thus, the size of the pull-up transistor may be reduced, thereby preventing a malfunction of the gate driving circuit when the gate driving circuit is operated under conditions of high temperature or low temperature.

Abstract translation: 在具有栅极驱动电路的栅极驱动电路和显示装置中，将多个相互依次连接并依次输出栅极信号的多级中的当前级的上拉晶体管拉起当前的栅极信号 通过输出端子输出到栅极导通电压。 缓冲晶体管连接到上拉晶体管的控制端，以接收来自前一级的先前输出信号并接通上拉晶体管。 缓冲晶体管具有的电荷率约为上拉晶体管的充电能力的两倍或更大。 因此，可以减小上拉晶体管的尺寸，从而当栅极驱动电路在高温或低温条件下工作时，防止栅极驱动电路的故障。

公开(公告)号：US20110221988A1

公开(公告)日：2011-09-15

申请号：US12900436

申请日：2010-10-07

Applicant: Se-Hyoung Cho ,  Dong-Gyu Kim ,  Mee-Hye Jung ,  Dong-Hyeon Ki ,  Seung-Soo Baek ,  Hye-Seok Na

Inventor： Se-Hyoung Cho ,  Dong-Gyu Kim ,  Mee-Hye Jung ,  Dong-Hyeon Ki ,  Seung-Soo Baek ,  Hye-Seok Na

IPC: G02F1/1343

CPC classification number: G02F1/1395 ,  G02F1/134363 ,  G02F1/136213 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2300/0443 ,  G09G2300/0447

Abstract: A liquid crystal display includes first and second substrates, and a liquid crystal layer disposed therebetween. First and second gate lines are disposed on the first substrate. First and second data lines, and a power line are disposed on the first substrate. A first switching element is connected to the first gate line and the first data line, a second switching element is connected to the first gate line and the power line, a third switching element is connected to the second gate line and the second data line, a first pixel electrode is connected to the first switching element, a second pixel electrode is connected to the second switching element, a third pixel electrode is connected to the second switching element, and a fourth pixel electrode is connected to the third switching element, and a gate-on voltage can be simultaneously applied to the first and second gate lines.

Abstract translation: 液晶显示器包括第一和第二基板以及设置在其间的液晶层。 第一和第二栅极线设置在第一基板上。 第一和第二数据线，以及电源线设置在第一基板上。 第一开关元件连接到第一栅极线和第一数据线，第二开关元件连接到第一栅极线和电源线，第三开关元件连接到第二栅极线和第二数据线， 第一像素电极连接到第一开关元件，第二像素电极连接到第二开关元件，第三像素电极连接到第二开关元件，第四像素电极连接到第三开关元件，以及 栅极导通电压可以同时施加到第一和第二栅极线。

公开(公告)号：US07851835B2

公开(公告)日：2010-12-14

申请号：US11494257

申请日：2006-07-27

Applicant: Shin-Tack Kang ,  Dong-Hyeon Ki ,  Sung-Man Kim ,  Sang-Hoon Lee

Inventor： Shin-Tack Kang ,  Dong-Hyeon Ki ,  Sung-Man Kim ,  Sang-Hoon Lee

IPC: H01L31/062

CPC classification number: G02F1/136227 ,  G02F1/13458 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288 ,  H01L29/41733

Abstract: A display substrate includes a substrate, a first insulating layer, an undercut compensating member, a first electrode, a second insulating layer and a first conductive pattern. The first insulating layer is formed on the substrate. The undercut compensating member is formed on the first insulating layer. The undercut compensating member has an etching rate smaller than that of the first insulating layer. The first electrode is formed on a portion of the undercut compensating member. The second insulating layer is formed on the first insulating layer. The second insulating layer has a contact hole through which a portion of the first electrode and a remaining portion of the undercut compensating member. The first conductive pattern electrically connected to the first electrode through the contact hole.

Abstract translation: 显示基板包括基板，第一绝缘层，底切补偿元件，第一电极，第二绝缘层和第一导电图案。 第一绝缘层形成在基板上。 底切补偿部件形成在第一绝缘层上。 底切补偿构件的蚀刻速率小于第一绝缘层的蚀刻速率。 第一电极形成在底切补偿部件的一部分上。 第二绝缘层形成在第一绝缘层上。 第二绝缘层具有接触孔，第一电极的一部分和底切补偿部件的剩余部分穿过该接触孔。 第一导电图案通过接触孔与第一电极电连接。

公开(公告)号：US20100090995A1

公开(公告)日：2010-04-15

申请号：US12577614

申请日：2009-10-12

Applicant: Chae-Woo CHUNG ,  Jae-Hyun Cho ,  Jeong-Uk Heo ,  Sun-Kyu Son ,  Dong-Hyeon Ki

Inventor： Chae-Woo CHUNG ,  Jae-Hyun Cho ,  Jeong-Uk Heo ,  Sun-Kyu Son ,  Dong-Hyeon Ki

IPC: G09G5/00 ,  G09G3/20

CPC classification number: G02F1/13336 ,  G02F1/1339 ,  G02F1/13452 ,  G02F2001/133317 ,  G02F2001/133322 ,  G02F2001/13398 ,  G02F2202/04 ,  H05K1/147

Abstract: A display apparatus and a multi-display apparatus having larger display areas. The display apparatus includes a first insulating substrate, as well as a plurality of gate lines and a plurality of data lines on the first insulating substrate, where the plurality of gate lines is arranged to intersect the plurality of data lines. A plurality of storage electrode lines is arranged substantially parallel to the plurality of gate lines. A gate drive chip is mounted off of the first insulating substrate and electrically connected to the plurality of gate lines and the plurality of storage electrode lines. The gate drive chip is configured to apply a gate voltage to the gate lines and a storage voltage to the storage electrode lines.

Abstract translation: 具有较大显示区域的显示装置和多显示装置。 显示装置包括第一绝缘基板，以及多个栅极线和在第一绝缘基板上的多条数据线，其中多条栅极线布置成与多条数据线相交。 多个存储电极线被布置成基本上平行于多条栅极线。 栅极驱动芯片安装在第一绝缘基板之外并电连接到多条栅极线和多条存储电极线。 栅极驱动芯片被配置为向栅极线施加栅极电压并将存储电压施加到存储电极线。

公开(公告)号：US20050208711A1

公开(公告)日：2005-09-22

申请号：US11126305

申请日：2005-05-11

Applicant: Woon-Yong Park ,  Hyeon-Hwan Kim ,  Dong-Hyeon Ki

Inventor： Woon-Yong Park ,  Hyeon-Hwan Kim ,  Dong-Hyeon Ki

IPC: G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/00 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/66765 ,  G02F1/134363 ,  G02F1/13458 ,  G02F1/1368 ,  G02F2001/136231 ,  H01L27/12 ,  H01L29/78669

Abstract: A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside. At this time, the etching is performed after an assembly process where a second substrate is arranged to face the first substrate and assembled together and the passivation layer and the gate insulating layer are exposed outside of the second substrate.

Abstract translation: 制造液晶显示器用薄膜阵列基板的方法包括在第一基板上形成栅线组合体和公共电极线组合体的工序。 栅极线组件包括多个栅极线和栅极焊盘，并且公共电极线组件包括公共信号线和公共电极。 此后，在第一基板上形成栅极绝缘层，并且在栅极绝缘层上形成半导体图案和欧姆接触图案。 然后在第一基板上形成数据线组件和像素电极。 数据线组件包括多条数据线，数据焊盘以及源极和漏极。 像素电极在平行于公共电极的同时连接到漏电极。 在衬底上形成钝化层。 蚀刻钝化层和栅极绝缘层，使得栅极焊盘和数据焊盘暴露于外部。 此时，在将第二基板布置成面对第一基板并组装在一起并且钝化层和栅极绝缘层暴露在第二基板外部的组装工艺之后进行蚀刻。

公开(公告)号：US06876405B1

公开(公告)日：2005-04-05

申请号：US10626767

申请日：2003-07-25

Applicant: Woon-Yong Park ,  Hyeon-Hwan Kim ,  Dong-Hyeon Ki

Inventor： Woon-Yong Park ,  Hyeon-Hwan Kim ,  Dong-Hyeon Ki

IPC: G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/786 ,  G02F1/136

CPC classification number: H01L29/66765 ,  G02F1/134363 ,  G02F1/13458 ,  G02F1/1368 ,  G02F2001/136231 ,  H01L29/78669

Abstract: A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside. At this time, the etching is performed after an assembly process where a second substrate is arranged to face the first substrate and assembled together and the passivation layer and the gate insulating layer are exposed outside of the second substrate.

Abstract translation: 制造液晶显示器用薄膜阵列基板的方法包括在第一基板上形成栅线组合体和公共电极线组合体的工序。 栅极线组件包括多个栅极线和栅极焊盘，并且公共电极线组件包括公共信号线和公共电极。 此后，在第一基板上形成栅极绝缘层，并且在栅极绝缘层上形成半导体图案和欧姆接触图案。 然后在第一基板上形成数据线组件和像素电极。 数据线组件包括多条数据线，数据焊盘以及源极和漏极。 像素电极在平行于公共电极的同时连接到漏电极。 在衬底上形成钝化层。 蚀刻钝化层和栅极绝缘层，使得栅极焊盘和数据焊盘暴露于外部。 此时，在将第二基板布置成面对第一基板并组装在一起并且钝化层和栅极绝缘层暴露在第二基板外部的组装工艺之后进行蚀刻。

公开(公告)号：US09311842B2

公开(公告)日：2016-04-12

申请号：US13410766

申请日：2012-03-02

Applicant: Seung-Soo Baek ,  Se Hyoung Cho ,  Dong-Gyu Kim ,  Dong-Hyeon Ki

Inventor： Seung-Soo Baek ,  Se Hyoung Cho ,  Dong-Gyu Kim ,  Dong-Hyeon Ki

IPC: G09G3/20 ,  G09G3/32 ,  G09G3/36

CPC classification number: G09G3/2092 ,  G09G3/2022 ,  G09G3/3266 ,  G09G3/3674 ,  G09G2300/0408 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0281 ,  G09G2310/0286

Abstract: A display device includes: a display panel including a display area, and a peripheral area disposed in the vicinity of the display area; a scan driver including a plurality of stages integrated on the peripheral area; a plurality of gate lines connected to the plurality of stages, respectively; and a plurality of pixel rows in the display area and connected with the plurality of gate lines, respectively. The plurality of stages and the plurality of pixel rows are each arranged in a first direction in a line, the peripheral area includes a fan-out region between the plurality of stages and the plurality of pixel rows, and at least one of the plurality of gate lines in the fan-out region is inclined with respect to the first direction, and a second direction perpendicular to the first direction.

Abstract translation: 显示装置包括：显示面板，包括显示区域和设置在显示区域附近的周边区域; 扫描驱动器，其包括集成在所述外围区域上的多个级; 分别连接到所述多个级的多个栅极线; 以及显示区域中的多个像素行并分别与多个栅极线连接。 所述多个级和所述多个像素行分别沿着第一方向排列，所述周边区域包括所述多个级与所述多个像素行之间的扇出区域，并且所述多个级和所述多个像素行中的至少一个 扇出区域中的栅极线相对于第一方向倾斜，并且垂直于第一方向的第二方向倾斜。

公开(公告)号：US08027004B2

公开(公告)日：2011-09-27

申请号：US11881382

申请日：2007-07-25

Applicant: Ji-Hyun Kwon ,  Byoung-Sun Na ,  Dong-Hyeon Ki ,  Soon-Il Ahn

Inventor： Ji-Hyun Kwon ,  Byoung-Sun Na ,  Dong-Hyeon Ki ,  Soon-Il Ahn

IPC: G02F1/1343

CPC classification number: G02F1/134336 ,  G02F1/133707 ,  G02F1/13624 ,  G02F2001/133397 ,  G02F2001/13373 ,  G02F2001/134345

Abstract: A liquid crystal display according to an embodiment of the invention includes a substrate, a plurality of gate lines formed on the substrate, a plurality of data lines formed on the substrate to intersect the gate lines, and a plurality of pixel electrodes formed on the substrate. In the liquid crystal display, the pixel electrode includes a first main side substantially parallel with the gate line, a second main side substantially parallel with the data line, a first oblique side making a first oblique angle with respect to the first and second main sides, and a second oblique side making a second oblique angle with respect to the first and second main sides. The first oblique angle and the second oblique angle are different from each other.

Abstract translation: 根据本发明实施例的液晶显示器包括基板，形成在基板上的多个栅极线，形成在基板上的与栅极线相交的多条数据线，以及形成在基板上的多个像素电极 。 在液晶显示器中，像素电极包括基本上平行于栅极线的第一主侧，与数据线大致平行的第二主侧，相对于第一和第二主侧产生第一倾斜角的第一斜面 以及相对于第一和第二主侧面成第二倾斜角的第二倾斜面。 第一倾斜角和第二倾斜角彼此不同。