公开(公告)号：US07130003B2

公开(公告)日：2006-10-31

申请号：US11126305

申请日：2005-05-11

申请人： Woon-Yong Park ,  Hyeon-Hwan Kim ,  Dong-Hyeon Ki

发明人： Woon-Yong Park ,  Hyeon-Hwan Kim ,  Dong-Hyeon Ki

IPC分类号： G02F1/1333 ,  G02F1/1343 ,  H01L21/00

CPC分类号： H01L29/66765 ,  G02F1/134363 ,  G02F1/13458 ,  G02F1/1368 ,  G02F2001/136231 ,  H01L27/12 ,  H01L29/78669

摘要： A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside. At this time, the etching is performed after an assembly process where a second substrate is arranged to face the first substrate and assembled together and the passivation layer and the gate insulating layer are exposed outside of the second substrate.

公开(公告)号：US06678018B2

公开(公告)日：2004-01-13

申请号：US09779705

申请日：2001-02-09

申请人： Woon-Yong Park ,  Hyeon-Hwan Kim ,  Dong-Hyeon Ki

发明人： Woon-Yong Park ,  Hyeon-Hwan Kim ,  Dong-Hyeon Ki

IPC分类号： G02F1136

CPC分类号： H01L29/66765 ,  G02F1/134363 ,  G02F1/13458 ,  G02F1/1368 ,  G02F2001/136231 ,  H01L27/12 ,  H01L29/78669

摘要： A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside. At this time, the etching is performed after an assembly process where a second substrate is arranged to face the first substrate and assembled together and the passivation layer and the gate insulating layer are exposed outside of the second substrate.

摘要翻译： 制造液晶显示器用薄膜阵列基板的方法包括在第一基板上形成栅线组合体和公共电极线组合体的工序。 栅极线组件包括多个栅极线和栅极焊盘，并且公共电极线组件包括公共信号线和公共电极。 此后，在第一基板上形成栅极绝缘层，并且在栅极绝缘层上形成半导体图案和欧姆接触图案。 然后在第一基板上形成数据线组件和像素电极。 数据线组件包括多条数据线，数据焊盘以及源极和漏极。 像素电极在平行于公共电极的同时连接到漏电极。 在衬底上形成钝化层。 蚀刻钝化层和栅极绝缘层，使得栅极焊盘和数据焊盘暴露于外部。 此时，在将第二基板布置成面对第一基板并组装在一起并且钝化层和栅极绝缘层暴露在第二基板外部的组装工艺之后进行蚀刻。

公开(公告)号：US06906776B2

公开(公告)日：2005-06-14

申请号：US10626738

申请日：2003-07-25

申请人： Woon-Yong Park ,  Hyeon-Hwan Kim ,  Dong-Hyeon Ki

发明人： Woon-Yong Park ,  Hyeon-Hwan Kim ,  Dong-Hyeon Ki

IPC分类号： G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/00 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  G02F1/13

CPC分类号： H01L29/66765 ,  G02F1/134363 ,  G02F1/13458 ,  G02F1/1368 ,  G02F2001/136231 ,  H01L27/12 ,  H01L29/78669

摘要： A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside. At this time, the etching is performed after an assembly process where a second substrate is arranged to face the first substrate and assembled together and the passivation layer and the gate insulating layer are exposed outside of the second substrate.

摘要翻译： 制造液晶显示器用薄膜阵列基板的方法包括在第一基板上形成栅线组合体和公共电极线组合体的工序。 栅极线组件包括多个栅极线和栅极焊盘，并且公共电极线组件包括公共信号线和公共电极。 此后，在第一基板上形成栅极绝缘层，并且在栅极绝缘层上形成半导体图案和欧姆接触图案。 然后在第一基板上形成数据线组件和像素电极。 数据线组件包括多条数据线，数据焊盘以及源极和漏极。 像素电极在平行于公共电极的同时连接到漏电极。 在衬底上形成钝化层。 蚀刻钝化层和栅极绝缘层，使得栅极焊盘和数据焊盘暴露于外部。 此时，在将第二基板布置成面对第一基板并组装在一起并且钝化层和栅极绝缘层暴露在第二基板外部的组装工艺之后进行蚀刻。

公开(公告)号：US20050208711A1

公开(公告)日：2005-09-22

申请号：US11126305

申请日：2005-05-11

申请人： Woon-Yong Park ,  Hyeon-Hwan Kim ,  Dong-Hyeon Ki

发明人： Woon-Yong Park ,  Hyeon-Hwan Kim ,  Dong-Hyeon Ki

IPC分类号： G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/00 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/66765 ,  G02F1/134363 ,  G02F1/13458 ,  G02F1/1368 ,  G02F2001/136231 ,  H01L27/12 ,  H01L29/78669

摘要： A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside. At this time, the etching is performed after an assembly process where a second substrate is arranged to face the first substrate and assembled together and the passivation layer and the gate insulating layer are exposed outside of the second substrate.

摘要翻译： 制造液晶显示器用薄膜阵列基板的方法包括在第一基板上形成栅线组合体和公共电极线组合体的工序。 栅极线组件包括多个栅极线和栅极焊盘，并且公共电极线组件包括公共信号线和公共电极。 此后，在第一基板上形成栅极绝缘层，并且在栅极绝缘层上形成半导体图案和欧姆接触图案。 然后在第一基板上形成数据线组件和像素电极。 数据线组件包括多条数据线，数据焊盘以及源极和漏极。 像素电极在平行于公共电极的同时连接到漏电极。 在衬底上形成钝化层。 蚀刻钝化层和栅极绝缘层，使得栅极焊盘和数据焊盘暴露于外部。 此时，在将第二基板布置成面对第一基板并组装在一起并且钝化层和栅极绝缘层暴露在第二基板外部的组装工艺之后进行蚀刻。

公开(公告)号：US06876405B1

公开(公告)日：2005-04-05

申请号：US10626767

申请日：2003-07-25

申请人： Woon-Yong Park ,  Hyeon-Hwan Kim ,  Dong-Hyeon Ki

发明人： Woon-Yong Park ,  Hyeon-Hwan Kim ,  Dong-Hyeon Ki

IPC分类号： G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/786 ,  G02F1/136

CPC分类号： H01L29/66765 ,  G02F1/134363 ,  G02F1/13458 ,  G02F1/1368 ,  G02F2001/136231 ,  H01L29/78669

摘要： A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside. At this time, the etching is performed after an assembly process where a second substrate is arranged to face the first substrate and assembled together and the passivation layer and the gate insulating layer are exposed outside of the second substrate.

摘要翻译： 制造液晶显示器用薄膜阵列基板的方法包括在第一基板上形成栅线组合体和公共电极线组合体的工序。 栅极线组件包括多个栅极线和栅极焊盘，并且公共电极线组件包括公共信号线和公共电极。 此后，在第一基板上形成栅极绝缘层，并且在栅极绝缘层上形成半导体图案和欧姆接触图案。 然后在第一基板上形成数据线组件和像素电极。 数据线组件包括多条数据线，数据焊盘以及源极和漏极。 像素电极在平行于公共电极的同时连接到漏电极。 在衬底上形成钝化层。 蚀刻钝化层和栅极绝缘层，使得栅极焊盘和数据焊盘暴露于外部。 此时，在将第二基板布置成面对第一基板并组装在一起并且钝化层和栅极绝缘层暴露在第二基板外部的组装工艺之后进行蚀刻。

公开(公告)号：US06441401B1

公开(公告)日：2002-08-27

申请号：US09527803

申请日：2000-03-17

申请人： Cheol-Soo Jung ,  Young-Sun Kim ,  Ho-Joon Lee ,  Yeong-Hwan Cho ,  Hyeon-Hwan Kim ,  Bung-Hyuk Min ,  Woon-Yong Park ,  Il-Gon Kim ,  Jang-Soo Kim ,  Jin-Oh Kwag ,  Seog-Chae Lee

发明人： Cheol-Soo Jung ,  Young-Sun Kim ,  Ho-Joon Lee ,  Yeong-Hwan Cho ,  Hyeon-Hwan Kim ,  Bung-Hyuk Min ,  Woon-Yong Park ,  Il-Gon Kim ,  Jang-Soo Kim ,  Jin-Oh Kwag ,  Seog-Chae Lee

IPC分类号： H01L2900

CPC分类号： G02F1/136259 ,  G02F2001/136263 ,  G02F2001/136272 ,  H01L27/12

摘要： A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line. A redundant repair line overlaps and is insulated from the storage wire at one end and overlaps the storage wire or the gate wire of a neighboring pixel at the other end is formed in the same layer as the data wire. Also, a storage wire connection portion connecting the storage wires of a neighboring pixel is formed in the same layer as the pixel electrode. In this structure, if portions of the gate wire or the data wire are disconnected, the portions overlapping the disconnected wire, the storage wire, and the redundant repair line are shorted to repair an open wire defect.

摘要翻译： 在绝缘基板上形成沿水平方向延伸的栅极线，并且垂直于限定矩阵阵列的像素的栅极线形成数据线。 通过数据线接收图像信号的像素电极形成在像素中，并且形成具有连接到栅极线的栅电极，连接到数据线的源电极和连接到像素电极的漏电极的薄膜晶体管 在栅极线和数据线相交的部分。 包括在水平方向上存储电极线的存储线，连接到存储电极线的存储电极以及连接相邻像素的存储电极的至少一个存储电极连接部分沿与栅极线相同的方向形成。 冗余维修线在一端重叠并与存储线绝缘，并与存储线重叠，另一端的相邻像素的栅极线形成在与数据线相同的层中。 此外，连接相邻像素的存储线的存储线连接部分形成在与像素电极相同的层中。 在这种结构中，如果栅极线或数据线的部分断开，与断开的线，存储线和冗余修复线重叠的部分短路以修复开路的线缺陷。

公开(公告)号：US07291860B2

公开(公告)日：2007-11-06

申请号：US10699791

申请日：2003-11-04

申请人： Cheol-Soo Jung ,  Young-Sun Kim ,  Ho-Joon Lee ,  Yeong-Hwan Cho ,  Hyeon-Hwan Kim ,  Bung-Hyuk Min ,  Woon-Yong Park ,  Il-Gon Kim ,  Jang-Soo Kim ,  Jin-Oh Kwag ,  Seog-Chae Lee

发明人： Cheol-Soo Jung ,  Young-Sun Kim ,  Ho-Joon Lee ,  Yeong-Hwan Cho ,  Hyeon-Hwan Kim ,  Bung-Hyuk Min ,  Woon-Yong Park ,  Il-Gon Kim ,  Jang-Soo Kim ,  Jin-Oh Kwag ,  Seog-Chae Lee

IPC分类号： H01L31/00

CPC分类号： G02F1/136259 ,  G02F2001/136263 ,  G02F2001/136272 ,  H01L27/12

摘要： A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line. A redundant repair line overlaps and is insulated from the storage wire at one end and overlaps the storage wire or the gate wire of a neighboring pixel at the other end is formed in the same layer as the data wire. Also, a storage wire connection portion connecting the storage wires of a neighboring pixel is formed in the same layer as the pixel electrode. In this structure, if portions of the gate wire or the data wire are disconnected, the portions overlapping the disconnected wire, the storage wire, and the redundant repair line are shorted to repair an open wire defect.

摘要翻译： 在绝缘基板上形成沿水平方向延伸的栅极线，并且垂直于限定矩阵阵列的像素的栅极线形成数据线。 通过数据线接收图像信号的像素电极形成在像素中，并且形成具有连接到栅极线的栅电极，连接到数据线的源电极和连接到像素电极的漏电极的薄膜晶体管 在栅极线和数据线相交的部分。 包括在水平方向上存储电极线的存储线，连接到存储电极线的存储电极，以及连接相邻像素的存储电极的至少一个存储电极连接部分以与栅极线相同的方向形成。 冗余修复线与存储线在一端重叠并与存储线绝缘，并与存储线重叠，另一端的相邻像素的栅极线形成在与数据线相同的层中。 此外，连接相邻像素的存储线的存储线连接部分形成在与像素电极相同的层中。 在这种结构中，如果栅极线或数据线的部分断开，与断开的线，存储线和冗余修复线重叠的部分短路以修复开路的线缺陷。

公开(公告)号：US06657231B2

公开(公告)日：2003-12-02

申请号：US10171777

申请日：2002-06-17

申请人： Cheol-Soo Jung ,  Young-Sun Kim ,  Ho-Joon Lee ,  Yeong-Hwan Cho ,  Hyeon-Hwan Kim ,  Bung-Hyuk Min ,  Woon-Yong Park ,  Il-Gon Kim ,  Jang-Soo Kim ,  Jin-Oh Kwag ,  Seog-Chae Lee

发明人： Cheol-Soo Jung ,  Young-Sun Kim ,  Ho-Joon Lee ,  Yeong-Hwan Cho ,  Hyeon-Hwan Kim ,  Bung-Hyuk Min ,  Woon-Yong Park ,  Il-Gon Kim ,  Jang-Soo Kim ,  Jin-Oh Kwag ,  Seog-Chae Lee

IPC分类号： H01L2904

CPC分类号： G02F1/136259 ,  G02F2001/136263 ,  G02F2001/136272 ,  H01L27/12

摘要： A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line. A redundant repair line overlaps and is insulated from the storage wire at one end and overlaps the storage wire or the gate wire of a neighboring pixel at the other end is formed in the same layer as the data wire. Also, a storage wire connection portion connecting the storage wires of a neighboring pixel is formed in the same layer as the pixel electrode. In this structure, if portions of the gate wire or the data wire are disconnected, the portions overlapping the disconnected wire, the storage wire, and the redundant repair line are shorted to repair an open wire defect.

公开(公告)号：US09401118B2

公开(公告)日：2016-07-26

申请号：US12604692

申请日：2009-10-23

申请人： Sung-Man Kim ,  Hong-Woo Lee ,  Jong-Hwan Lee ,  Hyeon-Hwan Kim ,  Jong-Hyuk Lee

发明人： Sung-Man Kim ,  Hong-Woo Lee ,  Jong-Hwan Lee ,  Hyeon-Hwan Kim ,  Jong-Hyuk Lee

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2300/0443 ,  G09G2300/0465 ,  G09G2300/0809 ,  G09G2310/0202 ,  G09G2320/0233 ,  G09G2320/0247 ,  G09G2320/0666

摘要： A display apparatus includes: a plurality of pixel blocks, each pixel block of the plurality of pixel blocks including a first pixel electrode connected to a first switching element and a second pixel electrode connected to a second switching element; gate lines which extend along a first direction and include a first gate line connected to the first switching element and a second gate line connected to the second switching element; and data lines which extend along a second direction intersecting the first direction. A gate voltage is applied to the first gate line before the second gate line, and the first pixel electrode of each of the pixel blocks displays a same color.

摘要翻译： 显示装置包括：多个像素块，所述多个像素块中的每个像素块包括连接到第一开关元件的第一像素电极和连接到第二开关元件的第二像素电极; 栅极线，沿着第一方向延伸并且包括连接到第一开关元件的第一栅极线和连接到第二开关元件的第二栅极线; 以及沿着与第一方向相交的第二方向延伸的数据线。 栅极电压施加到第二栅极线之前的第一栅极线，并且每个像素块的第一像素电极显示相同的颜色。

公开(公告)号：US08306177B2

公开(公告)日：2012-11-06

申请号：US12575895

申请日：2009-10-08

申请人： Hong-Woo Lee ,  Sung-Man Kim ,  Jong-Hyuk Lee ,  Jong-Hwan Lee ,  Hyeon-Hwan Kim ,  Sang-Moon Moh ,  Jeong-Il Kim ,  Yeon-Kyu Moon

发明人： Hong-Woo Lee ,  Sung-Man Kim ,  Jong-Hyuk Lee ,  Jong-Hwan Lee ,  Hyeon-Hwan Kim ,  Sang-Moon Moh ,  Jeong-Il Kim ,  Yeon-Kyu Moon

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2300/0408

摘要： A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.

摘要翻译： 上拉驱动部分通过响应于前一级或垂直启动信号之一接收导通电压而将第一节点的信号保持在高电平。 上拉部分响应于第一节点的信号通过输出端子输出时钟信号。 当第一节点的信号分别为低或高时，第一保持部件将第二节点的信号保持在高电平或低电平。 第二保持部分响应于第二节点的信号或延迟和反相的时钟信号，将第一节点的信号和输出端的信号保持在接地电压。