公开(公告)号：US20050265073A1

公开(公告)日：2005-12-01

申请号：US10957307

申请日：2004-09-30

申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/06 ,  G11C16/12 ,  G11C16/34 ,  G11C29/00 ,  G11C29/12

CPC分类号： G11C16/12 ,  G11C16/3454 ,  G11C16/3459

摘要： A non-volatile memory device includes a word line voltage generator circuit for generating a word line voltage to be supplied to a selected row in response to step control signals and a program controller for sequentially activating the step control signals during a program cycle. During the program cycle, the word line voltage generator circuit controls the increment of the word line voltage differently according to the mode of operation, namely, a test mode or a normal mode. Thus test time can be shortened.

摘要翻译： 非易失性存储器件包括字线电压发生器电路，用于响应于步进控制信号产生要提供给选定行的字线电压;以及程序控制器，用于在编程周期期间顺序激活步进控制信号。 在编程周期中，字线电压发生器电路根据操作模式，即测试模式或正常模式，不同地控制字线电压的增量。 因此可以缩短测试时间。

公开(公告)号：US07596022B2

公开(公告)日：2009-09-29

申请号：US11848014

申请日：2007-08-30

申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C2211/5646

摘要： A method for programming multi-level non-volatile memory. A plurality of multi-bit storage cells capable of storing different levels of charge usable to represent data represented by a least significant bits (LSBs) and a most significant bits (MSBs) are programmed first with LSBs and then with MSBs. The programmed storage cells have a threshold voltage lower than a voltage VR1 to store a first value, greater than VR1 and lower than a voltage VR2 to store a second value, and greater than VR2 and lower than a voltage VR3 to store a third value. Each of the cells has a threshold voltage greater than a voltage VR3 when it is desired that the storage cell store a fourth value. VR1 is less than VR2 which is less than VR3. The flag cell is programmed to have a threshold voltage greater than VR3 to indicate that the MSBs have been programmed.

摘要翻译： 一种用于编程多级非易失性存储器的方法。 能够存储可用于表示由最低有效位（LSB）和最高有效位（MSB）表示的数据的不同电荷电平的多个多位存储单元首先用LSB编程，然后用MSB编程。 编程存储单元具有低于电压VR1的阈值电压，以存储大于VR1且低于电压VR2的第一值以存储第二值，并且大于VR2且低于电压VR3以存储第三值。 当期望存储单元存储第四值时，每个单元具有大于电压VR3的阈值电压。 VR1小于小于VR3的VR2。 标志单元被编程为具有大于VR3的阈值电压以指示MSB已被编程。

公开(公告)号：US20080019183A1

公开(公告)日：2008-01-24

申请号：US11833546

申请日：2007-08-03

申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC分类号： G11C16/02

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/08

摘要： Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a plurality of pass voltage switches. These switches have outputs electrically coupled by diodes to the plurality of word lines. Methods of programming flash memory devices include applying a pass voltage to a plurality of unselected word lines in a non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. The sequentially ramped program voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage.

摘要翻译： 闪存器件包括其中具有多个EEPROM串的NAND串的存储器阵列。 提供字线驱动程序以提高编程效率。 字线驱动器通过多个字线电耦合到存储器阵列。 字线驱动器包括多个通过电压开关。 这些开关具有由二极管电耦合到多个字线的输出。 编程闪速存储器件的方法包括在非易失性存储器阵列中向多个未选择的字线施加通过电压，同时将顺序斜坡的编程电压施加到非易失性存储器阵列中的选定字线。 顺序斜坡编程电压具有被字线驱动器钳位到不小于通过电压值的电平的最小值。

公开(公告)号：US07911850B2

公开(公告)日：2011-03-22

申请号：US12489641

申请日：2009-06-23

申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC分类号： G11C16/12 ,  G11C16/08

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/08

摘要： Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a plurality of pass voltage switches. These switches have outputs electrically coupled by diodes to the plurality of word lines. Methods of programming flash memory devices include applying a pass voltage to a plurality of unselected word lines in a non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. The sequentially ramped program voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage.

摘要翻译： 闪速存储器件包括其中具有多个EEPROM串的NAND串的存储器阵列。 提供字线驱动程序以提高编程效率。 字线驱动器通过多个字线电耦合到存储器阵列。 字线驱动器包括多个通过电压开关。 这些开关具有由二极管电耦合到多个字线的输出。 编程闪速存储器件的方法包括在非易失性存储器阵列中向多个未选择的字线施加通过电压，同时将顺序斜坡的编程电压施加到非易失性存储器阵列中的选定字线。 顺序斜坡编程电压具有被字线驱动器钳位到不小于通过电压值的电平的最小值。

公开(公告)号：US07567460B2

公开(公告)日：2009-07-28

申请号：US11833546

申请日：2007-08-03

申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC分类号： G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/08

摘要： Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a plurality of pass voltage switches. These switches have outputs electrically coupled by diodes to the plurality of word lines. Methods of programming flash memory devices include applying a pass voltage to a plurality of unselected word lines in a non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. The sequentially ramped program voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage.

摘要翻译： 闪存器件包括其中具有多个EEPROM串的NAND串的存储器阵列。 提供字线驱动程序以提高编程效率。 字线驱动器通过多个字线电耦合到存储器阵列。 字线驱动器包括多个通过电压开关。 这些开关具有由二极管电耦合到多个字线的输出。 编程闪速存储器件的方法包括在非易失性存储器阵列中向多个未选择的字线施加通过电压，同时将顺序斜坡的编程电压施加到非易失性存储器阵列中的选定字线。 顺序斜坡编程电压具有被字线驱动器钳位到不小于通过电压值的电平的最小值。

公开(公告)号：US07272047B2

公开(公告)日：2007-09-18

申请号：US11177842

申请日：2005-07-08

申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C7/00

CPC分类号： G11C8/08

摘要： Disclosed is a voltage dividing circuit reducing effects of a parasitic capacitance and a wordline voltage generating circuit including that. The voltage dividing circuit according to an aspect of the present invention includes a first resistor, a plurality of second resistors, and a selection means. The first resistor is connected between an output voltage node and a dividing voltage node. The plurality of second resistors are connectable between the dividing voltage node and a ground. The second resistors are sequentially selected in response to a step control signal and connected to ground. In order to reduce the sum of a parasitic capacitance existing in the second resistors, the resistors are arranged in groups, and the selection means connects only that group that contains a selected resistor to the dividing voltage node.

摘要翻译： 公开了一种降低寄生电容的影响的分压电路和包括其的字线电压发生电路。 根据本发明的一个方面的分压电路包括第一电阻器，多个第二电阻器和选择装置。 第一个电阻连接在输出电压节点和分压电压节点之间。 多个第二电阻器可以在分压电压节点和地之间连接。 第二电阻器响应于步进控制信号被顺序选择并连接到地。 为了减少存在于第二电阻器中的寄生电容的总和，电阻器被分组布置，并且选择装置仅将包含所选电阻器的组件连接到分压电压节点。

公开(公告)号：US07158418B2

公开(公告)日：2007-01-02

申请号：US10976383

申请日：2004-10-29

申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC分类号： G11C11/34

CPC分类号： G11C16/30 ,  G11C16/04 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/12005 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/1202

摘要： A non-volatile memory device includes a word line voltage generator circuit for generating a word line voltage to be supplied to a selected row in response to step control signals, and a program controller for generating the step control signals so that an increment of the word line voltage is varied according to the mode of operation, namely, a test mode or normal mode. Thus test time can be shortened.

摘要翻译： 非易失性存储器件包括字线电压发生器电路，用于响应于步进控制信号产生要提供给所选行的字线电压;以及程序控制器，用于产生步进控制信号，使得字的增量 线路电压根据操作模式，即测试模式或正常模式而变化。 因此可以缩短测试时间。

公开(公告)号：US20060092703A1

公开(公告)日：2006-05-04

申请号：US11205245

申请日：2005-08-16

申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/08

摘要： Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a plurality of pass voltage switches. These switches have outputs electrically coupled by diodes to the plurality of word lines. Methods of programming flash memory devices include applying a pass voltage to a plurality of unselected word lines in a non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. The sequentially ramped program voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage.

摘要翻译： 闪存器件包括其中具有多个EEPROM串的NAND串的存储器阵列。 提供字线驱动程序以提高编程效率。 字线驱动器通过多个字线电耦合到存储器阵列。 字线驱动器包括多个通过电压开关。 这些开关具有由二极管电耦合到多个字线的输出。 编程闪速存储器件的方法包括在非易失性存储器阵列中向多个未选择的字线施加通过电压，同时将顺序斜坡的编程电压施加到非易失性存储器阵列中的选定字线。 顺序斜坡编程电压具有被字线驱动器钳位到不小于通过电压值的电平的最小值。

公开(公告)号：US07038949B2

公开(公告)日：2006-05-02

申请号：US10957307

申请日：2004-09-30

申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC分类号： G11C16/06

CPC分类号： G11C16/12 ,  G11C16/3454 ,  G11C16/3459

摘要： A non-volatile memory device includes a word line voltage generator circuit for generating a word line voltage to be supplied to a selected row in response to step control signals and a program controller for sequentially activating the step control signals during a program cycle. During the program cycle, the word line voltage generator circuit controls the increment of the word line voltage differently according to the mode of operation, namely, a test mode or a normal mode. Thus test time can be shortened.

摘要翻译： 非易失性存储器件包括字线电压发生器电路，用于响应于步进控制信号产生要提供给选定行的字线电压;以及程序控制器，用于在编程周期期间顺序激活步进控制信号。 在编程周期中，字线电压发生器电路根据操作模式，即测试模式或正常模式，不同地控制字线电压的增量。 因此可以缩短测试时间。

公开(公告)号：US07508705B2

公开(公告)日：2009-03-24

申请号：US11847980

申请日：2007-08-30

申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC分类号： G11C16/04

CPC分类号： G11C16/3404

摘要： A method for programming multi-level non-volatile memory including at least one flag cell and a plurality of multi-bit storage cells. Each storage cell stores data of a least significant bit (LSB) and a most significant bit (MSB). The cells are programmed with LSB data such that programmed storage cells have a threshold voltage greater than VR1. The threshold voltage is modified to have a threshold voltage greater than VR2 for a third or fourth value. The cells are programmed with MSB data for a threshold voltage lower than a VR1 for a first value greater than VR1 and lower than VR2 for a second value, greater than VR2 and lower than VR3 for a third value, and greater than VR3 for a fourth value. VR1 is less than VR2 which is less than VR3. The flag cell is programmed to signal whether MSB data has been programmed.

摘要翻译： 一种用于编程包括至少一个标志单元和多个多位存储单元的多级非易失性存储器的方法。 每个存储单元存储最低有效位（LSB）和最高有效位（MSB）的数据。 单元被编程为LSB数据，使得编程的存储单元具有大于VR1的阈值电压。 对于第三或第四值，阈值电压被修改为具有大于VR2的阈值电压。 对于小于VR1的阈值电压，对于小于VR1的第一值并且对于第二值低于VR2的单元，对于第三值，单元格被编程为高于VR2且低于VR3，而对于第四值大于VR3 值。 VR1小于小于VR3的VR2。 标志单元被编程为通知MSB数据是否被编程。