公开(公告)号：US07338849B2

公开(公告)日：2008-03-04

申请号：US11261820

申请日：2005-10-28

Applicant: Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

Inventor： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC: H01L21/8238 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on the active regions. The first conductive layer patterns are spaced apart from each other in a lengthwise direction of the active regions. An insulating layer is conformally formed on the semiconductor substrate and the first conductive layer patterns. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns. The second conductive layer patterns cross the active regions and the isolation layer to overlap the first conductive layer patterns.

Abstract translation: 提供了制造闪速存储器件的方法和由此制造的闪存器件。 一种方法包括在半导体衬底中形成隔离层以在半导体衬底中限定多个平行的有源区。 在有源区上形成多个第一导电层图案。 第一导电层图案在活性区域的长度方向上彼此间隔开。 在半导体衬底和第一导电层图案上共形形成绝缘层。 在绝缘层上形成第二导电层。 图案化第二导电层直到绝缘层暴露以形成多个平行的第二导电层图案。 第二导电层图案与有源区和隔离层交叉，以与第一导电层图案重叠。

公开(公告)号：US08530954B2

公开(公告)日：2013-09-10

申请号：US12491529

申请日：2009-06-25

Applicant: Dong-Hyun Kim ,  Chang-Jin Kang

Inventor： Dong-Hyun Kim ,  Chang-Jin Kang

IPC: H01L29/792

CPC classification number: H01L21/28282

Abstract: Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.

Abstract translation: 非易失性存储器件包括在衬底的沟道区上的隧道绝缘层，隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。 第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。 第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。 栅电极位于第一阻挡层图案上。 第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

公开(公告)号：US07564094B2

公开(公告)日：2009-07-21

申请号：US12004985

申请日：2007-12-21

Applicant: Dong-Hyun Kim ,  Chang-Jin Kang

Inventor： Dong-Hyun Kim ,  Chang-Jin Kang

IPC: H01L21/8238

CPC classification number: H01L21/28282

Abstract: Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.

Abstract translation: 非易失性存储器件包括在衬底的沟道区上的隧道绝缘层，隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。 第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。 第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。 栅电极位于第一阻挡层图案上。 第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

公开(公告)号：US20090261405A1

公开(公告)日：2009-10-22

申请号：US12491529

申请日：2009-06-25

Applicant: Dong Hyun Kim ,  Chang-Jin Kang

Inventor： Dong Hyun Kim ,  Chang-Jin Kang

IPC: H01L29/792

CPC classification number: H01L21/28282

Abstract: Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.

Abstract translation: 非易失性存储器件包括在衬底的沟道区上的隧道绝缘层，隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。 第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。 第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。 栅电极位于第一阻挡层图案上。 第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

公开(公告)号：US20080199975A1

公开(公告)日：2008-08-21

申请号：US12032018

申请日：2008-02-15

Applicant: Min-Joon Park ,  Chang-Jin Kang ,  Dong-Hyun Kim

Inventor： Min-Joon Park ,  Chang-Jin Kang ,  Dong-Hyun Kim

IPC: H01L21/18 ,  H01L21/3065

CPC classification number: H01L27/11521 ,  H01L21/0206 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L29/40117

Abstract: Provided herein are methods of forming a metal oxide layer pattern on a substrate including providing a preliminary metal oxide layer on a substrate; etching the preliminary metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increases in a vertically downward direction; and etching the preliminary metal oxide layer pattern to form a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer. The present invention also provides methods of manufacturing a semiconductor device including forming a metal oxide layer and a first conductive layer on a substrate; etching the metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increase in a vertically downward direction; etching the first conductive layer to provide a first conductive layer pattern; and etching the preliminary metal oxide layer pattern to provide a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer pattern.

Abstract translation: 本文提供了在衬底上形成金属氧化物层图案的方法，包括在衬底上提供初步金属氧化物层; 蚀刻初始金属氧化物层以提供初步金属氧化物层图案，其中预备金属氧化物层图案的线宽在垂直向下的方向上逐渐增加; 并且以使得预备金属氧化物层的下部的线宽减小的方式蚀刻初步金属氧化物层图案以形成金属氧化物层图案。 本发明还提供了制造半导体器件的方法，包括在衬底上形成金属氧化物层和第一导电层; 蚀刻金属氧化物层以提供初步金属氧化物层图案，其中初始金属氧化物层图案的线宽在垂直向下的方向上逐渐增加; 蚀刻第一导电层以提供第一导电层图案; 并且蚀刻初步金属氧化物层图案以提供金属氧化物层图案，以便减小初步金属氧化物层图案的下部的线宽度。

公开(公告)号：US20080150008A1

公开(公告)日：2008-06-26

申请号：US12004985

申请日：2007-12-21

Applicant: Dong-Hyun Kim ,  Chang-Jin Kang

Inventor： Dong-Hyun Kim ,  Chang-Jin Kang

IPC: H01L29/792 ,  H01L21/28

CPC classification number: H01L21/28282

Abstract: Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.

Abstract translation: 非易失性存储器件包括在衬底的沟道区上的隧道绝缘层，隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。 第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。 第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。 栅电极位于第一阻挡层图案上。 第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

公开(公告)号：US20060094188A1

公开(公告)日：2006-05-04

申请号：US11261820

申请日：2005-10-28

Applicant: Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

Inventor： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on the active regions. The first conductive layer patterns are spaced apart from each other in a lengthwise direction of the active regions. An insulating layer is conformally formed on the semiconductor substrate and the first conductive layer patterns. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns. The second conductive layer patterns cross the active regions and the isolation layer to overlap the first conductive layer patterns.

Abstract translation: 提供了制造闪速存储器件的方法和由此制造的闪存器件。 一种方法包括在半导体衬底中形成隔离层以在半导体衬底中限定多个平行的有源区。 在有源区上形成多个第一导电层图案。 第一导电层图案在活性区域的长度方向上彼此间隔开。 在半导体衬底和第一导电层图案上共形形成绝缘层。 在绝缘层上形成第二导电层。 图案化第二导电层直到绝缘层暴露以形成多个平行的第二导电层图案。 第二导电层图案与有源区和隔离层交叉，以与第一导电层图案重叠。

公开(公告)号：US07763544B2

公开(公告)日：2010-07-27

申请号：US12496108

申请日：2009-07-01

Applicant: Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

Inventor： Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

IPC: H01L21/302

CPC classification number: H01L21/0331 ,  H01L21/0332 ,  H01L21/76897

Abstract: There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.

Abstract translation: 提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。 形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，以及形成硅锗（Si1-xGex）牺牲层 ，其具有等于或高于至少导电线结构的高度的高度，在基板的整个表面上。 然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。 使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。 然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

公开(公告)号：US07736970B2

公开(公告)日：2010-06-15

申请号：US11869400

申请日：2007-10-09

Applicant: Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

Inventor： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC: H01L21/8242

CPC classification number: H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Abstract translation: 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层， 选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

公开(公告)号：US07566659B2

公开(公告)日：2009-07-28

申请号：US11157435

申请日：2005-06-21

Applicant: Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

Inventor： Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

IPC: H01L21/44

CPC classification number: H01L21/0331 ,  H01L21/0332 ,  H01L21/76897

Abstract: There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.

Abstract translation: 提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。 形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，以及形成硅锗（Si1-xGex）牺牲层 ，其具有等于或高于至少导电线结构的高度的高度，在基板的整个表面上。 然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。 使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。 然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。