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    Non-volatile memory devices including first and second blocking layer patterns
    5.
    发明授权
    Non-volatile memory devices including first and second blocking layer patterns 有权
    包括第一和第二阻挡层图案的非易失性存储器件

    公开(公告)号：US08530954B2

    公开(公告)日：2013-09-10

    申请号：US12491529

    申请日：2009-06-25

    申请人： Dong-Hyun Kim ,  Chang-Jin Kang

    发明人： Dong-Hyun Kim ,  Chang-Jin Kang

    IPC分类号： H01L29/792

    CPC分类号： H01L21/28282

    摘要： Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.

    摘要翻译： 非易失性存储器件包括在衬底的沟道区上的隧道绝缘层，隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。 第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。 第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。 栅电极位于第一阻挡层图案上。 第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

    Contact structures and semiconductor devices including the same
    6.
    发明授权
    Contact structures and semiconductor devices including the same 有权
    接触结构和包括其的半导体器件

    公开(公告)号：US08378497B2

    公开(公告)日：2013-02-19

    申请号：US12758946

    申请日：2010-04-13

    申请人： Seong-Goo Kim ,  Hyeong-Sun Hong ,  Dong-Hyun Kim ,  Nam-Jung Kang

    发明人： Seong-Goo Kim ,  Hyeong-Sun Hong ,  Dong-Hyun Kim ,  Nam-Jung Kang

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L29/4236 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876

    摘要： Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.

    摘要翻译： 在半导体器件中形成接触结构的方法包括提供包括有源区和跨越有源区的字线的半导体衬底。 在半导体衬底上形成第一层间电介质层。 形成延伸穿过第一层间电介质层的直接接触插塞以接触所选择的有源区域。 位线结构形成在第一层间电介质层上并且通过直接接触插塞与被选择的有源区域耦合的字线交叉。 在包括位线结构的半导体衬底上形成第二层间电介质层。 阻挡层图案形成为与位线结构平行延伸并进入第二层间电介质层。 掩模图形形成在第二层间介质层上的直接接触插塞的整个顶表面和位线结构上。 使用掩模图案蚀刻第二和第一层间电介质层，将掩模图案和位线结构作为蚀刻掩模形成埋入的接触孔，并且在埋入的接触孔中形成掩埋的接触插塞。

    Virtual measuring device and method
    7.
    发明授权
    Virtual measuring device and method 有权
    虚拟测量装置及方法

    公开(公告)号：US08266080B2

    公开(公告)日：2012-09-11

    申请号：US12354356

    申请日：2009-01-15

    申请人： Won-Hyouk Jang ,  Joo-Hwa Lee ,  Dong-Hyun Kim ,  Hyo-Jin Han ,  Kil-Ho Ok ,  Sung-Hoon Kim

    发明人： Won-Hyouk Jang ,  Joo-Hwa Lee ,  Dong-Hyun Kim ,  Hyo-Jin Han ,  Kil-Ho Ok ,  Sung-Hoon Kim

    IPC分类号： G06F15/18

    CPC分类号： G01B11/0641 ,  G01B11/0683 ,  H01L22/12 ,  H01L22/20

    摘要： A virtual measuring device and a method for measuring the deposition thickness of amorphous silicon being deposited on a substrate is disclosed, where the method of measuring the deposition thickness of amorphous silicon includes predicting and adapting operations. In the predicting operation, during a process of depositing the amorphous silicon to a substrate, the deposition thickness is predicted by multiplying a predicted deposition speed to a deposition time by using a prediction model expressing a relationship between a deposition speed and a plurality of process factors that are correlated with the deposition speed obtained from the deposition thickness and the deposition time, and the predicted deposition thickness is compared with the measured deposition thickness, so that the relationship between the plurality of process factors and the deposition speed in the prediction model is compensated according to the comparison difference.

    摘要翻译： 公开了一种用于测量沉积在衬底上的非晶硅的沉积厚度的虚拟测量装置和方法，其中测量非晶硅的沉积厚度的方法包括预测和适应操作。 在预测操作中，在将非晶硅沉积到衬底的过程中，通过使用表示沉积速度和多个工艺因素之间的关系的预测模型将预测的沉积速度乘以沉积时间来预测沉积厚度 与从沉积厚度和沉积时间获得的沉积速度相关联，并将预测的沉积厚度与测量的沉积厚度进行比较，使得多个工艺因素之间的关系和预测模型中的沉积速度被补偿 根据比较差异。

    FUEL CELL SYSTEM HAVING A REFORMER
    9.
    发明申请
    FUEL CELL SYSTEM HAVING A REFORMER 失效
    具有改造器的燃油电池系统

    公开(公告)号：US20110262820A1

    公开(公告)日：2011-10-27

    申请号：US12971437

    申请日：2010-12-17

    申请人： Hyun Kim ,  Dong-Rak Kim ,  Dong-Hyun Kim ,  Ming-Zi Hong ,  Woong-Ho Cho

    发明人： Hyun Kim ,  Dong-Rak Kim ,  Dong-Hyun Kim ,  Ming-Zi Hong ,  Woong-Ho Cho

    IPC分类号： H01M8/06

    CPC分类号： C01B3/384 ,  C01B3/323 ,  C01B2203/0233 ,  C01B2203/0283 ,  C01B2203/044 ,  C01B2203/0445 ,  C01B2203/047 ,  C01B2203/066 ,  C01B2203/0811 ,  C01B2203/1223 ,  C01B2203/1235 ,  H01M8/04007 ,  H01M8/04201 ,  H01M8/04253 ,  H01M8/0612 ,  H01M8/0668

    摘要： A fuel cell system includes a fuel cell stack, an oxidizer supply unit, a reformer, a fuel tank, and a water tank. The reformer generates a hydrogen-containing reformed gas reformed from hydrocarbon-based fuel and supplies it to the fuel cell stack. The fuel tank supplies the hydrocarbon-based fuel to the reformer. The water tank supplies water to the reformer. The reformer includes a reforming unit configured to have a reforming reaction generated therein, a combustion unit configured to supply heat energy to the reforming unit, and a carbon monoxide reduction unit configured to reduce the concentration of carbon monoxide in a reformed gas discharged from the reforming unit. A combustion gas pipe is connected to the combustion unit. A reformed gas pipe is disposed between the reforming unit and the carbon monoxide reduction unit. At least one of the combustion gas pipe and the reformed gas pipe is configured to pass through the inside of the water tank or to raise a temperature of the water tank through contact with the water tank, thereby preventing the freezing of the water tank.

    摘要翻译： 燃料电池系统包括燃料电池堆，氧化剂供应单元，重整器，燃料箱和水箱。 重整器产生从烃类燃料重整而成的含氢重整气体，并将其供给到燃料电池堆。 燃料箱向重整器供应烃类燃料。 水箱向改性机供水。 重整器包括：重整单元，其被配置为具有在其中产生的重整反应;燃烧单元，被配置为向重整单元供应热能;以及一氧化碳还原单元，被配置为减少从重整器排出的重整气体中的一氧化碳浓度 单元。 燃烧气体管道连接到燃烧单元。 重整气体管道设置在重整单元和一氧化碳减少单元之间。 燃烧气体管道和重整气体管道中的至少一个构造成通过水箱的内部，或者通过与水箱接触来提高水箱的温度，从而防止水箱的冻结。

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    10.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20100297840A1

    公开(公告)日：2010-11-25

    申请号：US12642496

    申请日：2009-12-18

    申请人： Tae-Han KIM ,  Dong-Hyun Kim

    发明人： Tae-Han KIM ,  Dong-Hyun Kim

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L29/4941

    摘要： A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, sequentially forming a silicon layer and a metal layer over the gate insulation layer, performing a first gate etching process to etch the metal layer using a gate hard mask layer, formed on the metal layer, as an etch barrier, and then partially etch the silicon layer, thereby forming a first pattern, performing a second gate etching process to partially etch the silicon layer, thereby forming an undercut beneath the metal layer, forming a capping layer on both sidewalls of the first pattern including the undercut, performing a third gate etching process to etch the silicon layer to expose the gate insulation layer using the gate hard mask layer and the capping layer as an etch barrier, thereby forming a second pattern, and performing a gate re-oxidation process.

    摘要翻译： 一种制造半导体器件的方法包括在衬底上形成栅极绝缘层，在栅极绝缘层上依次形成硅层和金属层，执行第一栅极蚀刻工艺以使用栅极硬掩模层来蚀刻金属层， 形成在金属层上，作为蚀刻阻挡层，然后部分地蚀刻硅层，由此形成第一图案，执行第二栅极蚀刻工艺以部分蚀刻硅层，从而在金属层下方形成底切，形成封盖 在包括底切的第一图案的两个侧壁上，执行第三栅极蚀刻工艺以蚀刻硅层，以使用栅极硬掩模层和封盖层作为蚀刻阻挡层来露出栅极绝缘层，从而形成第二图案， 并进行栅极再氧化处理。