公开(公告)号：US20110136311A1

公开(公告)日：2011-06-09

申请号：US13028654

申请日：2011-02-16

申请人： Dong-Suk SHIN ,  Ho Lee ,  Myung-Sun Kim

发明人： Dong-Suk SHIN ,  Ho Lee ,  Myung-Sun Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/1083 ,  H01L21/76267 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor device having a locally buried insulation layer and a method of manufacturing a semiconductor device having the same are provided, in which a gate electrode is formed on a substrate, and oxygen ions are implanted into an active region to form a locally buried insulation layer. An impurity layer is formed on the locally buried insulation layer to form a source/drain. A silicide layer is formed on the source/drain and on the gate electrode. The locally buried insulation layer can prevent junction leakage, decrease junction capacitance and prevent a critical voltage of an MOS transistor from increasing due to body bias, thereby to improve characteristics of the device.

摘要翻译： 提供了具有局部掩埋绝缘层的半导体器件及其制造方法，其中在基板上形成栅电极，并将氧离子注入有源区以形成局部掩埋的绝缘层 。 在局部掩埋的绝缘层上形成杂质层以形成源极/漏极。 在源极/漏极和栅电极上形成硅化物层。 局部埋入绝缘层可以防止结漏电，降低结电容，并防止MOS晶体管的临界电压由于体偏压而增加，从而改善器件的特性。

公开(公告)号：US20110201166A1

公开(公告)日：2011-08-18

申请号：US13021029

申请日：2011-02-04

申请人： Hoi-Sung CHUNG ,  Dong-Suk SHIN ,  Dong-Hyuk KIM ,  Jung-Shik HEO ,  Myung-Sun KIM

发明人： Hoi-Sung CHUNG ,  Dong-Suk SHIN ,  Dong-Hyuk KIM ,  Jung-Shik HEO ,  Myung-Sun KIM

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/30608 ,  H01L21/3086 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  Y10S438/938

摘要： A method of manufacturing a semiconductor device includes forming a gate electrode on a semiconductor substrate and a sidewall spacer on the gate electrode. Then, a portion of the semiconductor substrate at both sides of the sidewall spacer is partially etched to form a trench. A SiGe mixed crystal layer is formed in the trench. A silicon layer is formed on the SiGe mixed crystal layer. A portion of the silicon layer is partially etched using an etching solution having different etching rates in accordance with a crystal direction of a face of the silicon layer to form a capping layer including a silicon facet having an (111) inclined face.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成栅电极和在栅电极上形成侧壁间隔物。 然后，部分地蚀刻在侧壁间隔物的两侧的半导体衬底的一部分以形成沟槽。 在沟槽中形成SiGe混合晶体层。 在SiGe混晶层上形成硅层。 使用根据硅层的表面的晶体方向具有不同蚀刻速率的蚀刻溶液来部分蚀刻硅层的一部分，以形成包括具有（111）倾斜面的硅小面的覆盖层。

公开(公告)号：US20160064565A1

公开(公告)日：2016-03-03

申请号：US14938172

申请日：2015-11-11

申请人： Dong-Suk SHIN ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM ,  Nae-In LEE

发明人： Dong-Suk SHIN ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM ,  Nae-In LEE

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

公开(公告)号：US20160079424A1

公开(公告)日：2016-03-17

申请号：US14951932

申请日：2015-11-25

申请人： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

发明人： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/167

CPC分类号： H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

公开(公告)号：US20160087101A1

公开(公告)日：2016-03-24

申请号：US14955289

申请日：2015-12-01

申请人： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

发明人： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

摘要翻译： 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。 所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。 第二沟槽可以包括有源区的切口部分。

公开(公告)号：US20150214329A1

公开(公告)日：2015-07-30

申请号：US14680349

申请日：2015-04-07

申请人： Dong-Suk SHIN ,  Hyun-Chul KANG ,  Dong-Hyun ROH ,  Pan-Kwi PARK ,  Geo-Myung SHIN ,  Nae-In LEE ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM

发明人： Dong-Suk SHIN ,  Hyun-Chul KANG ,  Dong-Hyun ROH ,  Pan-Kwi PARK ,  Geo-Myung SHIN ,  Nae-In LEE ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM

IPC分类号： H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

摘要翻译： 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成沟槽，并且沟槽可以包括有源区的切口部分。 所述方法还可以包括在沟槽中形成嵌入的应力源。 嵌入式应力器可以包括下半导体层和上半导体层，其宽度比下半导体层的宽度窄。 上半导体层的一侧可以不与下半导体层的一侧对准，并且上半导体层的最上表面可以高于有源区的最上表面。

公开(公告)号：US20140141589A1

公开(公告)日：2014-05-22

申请号：US14033639

申请日：2013-09-23

申请人： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

发明人： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC分类号： H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

摘要翻译： 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。 所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。 第二沟槽可以包括有源区的切口部分。

公开(公告)号：US20100109729A1

公开(公告)日：2010-05-06

申请号：US12343859

申请日：2008-12-24

申请人： Dong-Suk SHIN

发明人： Dong-Suk SHIN

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K5/159 ,  H03K5/26

摘要： A duty cycle corrector includes a duty adjusting unit configured to adjust a duty cycle of an input clock in response to a duty correction code and generate an output clock, a duty detecting unit configured to measure a difference between a high pulse width and a low pulse width of the output clock and output a difference value, and an accumulating unit configured to accumulate the difference value to generate the duty correction code.

摘要翻译： 占空比校正器包括：占空比调整单元，被配置为响应于占空比校正码调整输入时钟的占空比并产生输出时钟;占空比检测单元，被配置为测量高脉冲宽度与低脉冲之间的差 输出时钟的宽度并输出差值;以及累加单元，被配置为累积差值以生成占空比校正码。

公开(公告)号：US20150318399A1

公开(公告)日：2015-11-05

申请号：US14600142

申请日：2015-01-20

申请人： Yeong-Jong JEONG ,  Jeong-Yun LEE ,  Geo-Myung SHIN ,  Dong-Suk SHIN ,  Si-Hyung LEE ,  Seo-Jin JEONG

发明人： Yeong-Jong JEONG ,  Jeong-Yun LEE ,  Geo-Myung SHIN ,  Dong-Suk SHIN ,  Si-Hyung LEE ,  Seo-Jin JEONG

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC分类号： H01L29/7848 ,  B82Y10/00 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/78696

摘要： A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.

摘要翻译： 一种半导体器件包括由场绝缘层限定并沿着第一方向延伸的第一多沟道有源图案，该第一多沟道有源图案包括第一部分，该第一部分具有在向上方向上进一步向上方突出的顶表面， 所述场绝缘层和所述第一部分的两侧上的第二部分，所述第二部分具有连续轮廓的侧壁和在所述场绝缘层的顶表面上向上方向突出的顶表面，并且在向上方向上突出 小于第一部分的顶表面的第一部分上的栅电极，在第一多通道有源图案的第一部分上并且沿着不同于第一方向的第二方向延伸的栅电极，以及在第一部分的第二部分上的第一源极/漏极区域 第一多通道有源图案并接触场绝缘层。

公开(公告)号：US20110267118A1

公开(公告)日：2011-11-03

申请号：US12938081

申请日：2010-11-02

申请人： Dong-Suk SHIN

发明人： Dong-Suk SHIN

IPC分类号： H03L7/06

CPC分类号： H03L7/0818

摘要： A delay locked loop (DLL) of a semiconductor integrated circuit includes a first delay line configured to variably delay a source clock signal and output a locked clock signal, a phase comparator configured to compare the phase of the source clock signal with the phase of a feedback clock signal, a second delay line configured to variably delay the locked clock signal, a first delay controller configured to control the first delay time of the first delay line, a second delay controller configured to control the minimum delay time of the second delay line, and an operation mode controller configured to control the first and second delay controllers in response to an output signal of the phase comparator, and switch operation modes of the first and second delay controllers depending on locking state of the delay lines.

摘要翻译： 半导体集成电路的延迟锁定环（DLL）包括：第一延迟线，被配置为可变地延迟源时钟信号并输出​​锁定的时钟信号;相位比较器，被配置为将源时钟信号的相位与 反馈时钟信号，被配置为可变延迟锁定的时钟信号的第二延迟线;配置成控制第一延迟线的第一延迟时间的第一延迟控制器，被配置为控制第二延迟线的最小延迟时间的第二延迟控制器 以及操作模式控制器，被配置为响应于相位比较器的输出信号来控制第一和第二延迟控制器，以及根据延迟线的锁定状态的第一和第二延迟控制器的切换操作模式。