公开(公告)号：US08598647B2

公开(公告)日：2013-12-03

申请号：US13291519

申请日：2011-11-08

申请人： Dongwoo Kim ,  Toshiro Nakanishi ,  SeungHyun Lim ,  Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn

发明人： Dongwoo Kim ,  Toshiro Nakanishi ,  SeungHyun Lim ,  Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn

IPC分类号： H01L29/788

CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor devices. The device includes conductive patterns stacked on a substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern includes a first doped region disposed adjacent to at least one of the conductive patterns, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

摘要翻译： 提供三维半导体器件。 该器件包括堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案包括邻近至少一个导电图案设置的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US20120112260A1

公开(公告)日：2012-05-10

申请号：US13291519

申请日：2011-11-08

申请人： Dongwoo Kim ,  Toshiro Nakanishi ,  SeungHyun Lim ,  Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn

发明人： Dongwoo Kim ,  Toshiro Nakanishi ,  SeungHyun Lim ,  Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn

IPC分类号： H01L29/788 ,  H01L29/78

CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor devices. The device includes conductive patterns stacked on a substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern includes a first doped region disposed adjacent to at least one of the conductive patterns, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

摘要翻译： 提供三维半导体器件。 该器件包括堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案包括邻近至少一个导电图案设置的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US08575682B2

公开(公告)日：2013-11-05

申请号：US13323452

申请日：2011-12-12

申请人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

发明人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC分类号： H01L29/66

CPC分类号： H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

摘要翻译： 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US20120153372A1

公开(公告)日：2012-06-21

申请号：US13323452

申请日：2011-12-12

申请人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

发明人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC分类号： H01L29/78

CPC分类号： H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

摘要翻译： 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US09490371B2

公开(公告)日：2016-11-08

申请号：US14539043

申请日：2014-11-12

申请人： Young-Jin Noh ,  Bio Kim ,  Kwangmin Park ,  Jaeyoung Ahn ,  SeungHyun Lim ,  JaeHo Choi ,  Jumi Yun ,  Ji-Hoon Choi

发明人： Young-Jin Noh ,  Bio Kim ,  Kwangmin Park ,  Jaeyoung Ahn ,  SeungHyun Lim ,  JaeHo Choi ,  Jumi Yun ,  Ji-Hoon Choi

IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L27/115

CPC分类号： H01L29/7926 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792

摘要： A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.

摘要翻译： 非易失性存储器件包括栅极结构，栅极结构包括垂直堆叠在衬底上的栅极间绝缘图案和介于栅间绝缘图案之间的栅极电极，通过栅极结构连接到衬底的垂直有源柱，电荷存储 垂直有源柱和栅电极之间的层，电荷存储层和垂直有源柱之间的隧道绝缘层，以及电荷存储层和栅电极之间的阻挡绝缘层。 电荷存储层包括分别与隔离绝缘层和隧道绝缘层相邻的第一和第二电荷存储层。 第一电荷存储层包括氮化硅层，第二电荷存储层包括氮氧化硅层。

公开(公告)号：US20150194440A1

公开(公告)日：2015-07-09

申请号：US14539043

申请日：2014-11-12

申请人： Young-Jin Noh ,  Bio Kim ,  Kwangmin Park ,  Jaeyoung Ahn ,  SeungHyun Lim ,  JaeHo Choi ,  Jumi Yun ,  Ji-Hoon Choi

发明人： Young-Jin Noh ,  Bio Kim ,  Kwangmin Park ,  Jaeyoung Ahn ,  SeungHyun Lim ,  JaeHo Choi ,  Jumi Yun ,  Ji-Hoon Choi

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L29/7926 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792

摘要： A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.

摘要翻译： 非易失性存储器件包括栅极结构，栅极结构包括垂直堆叠在衬底上的栅极间绝缘图案和介于栅间绝缘图案之间的栅极电极，通过栅极结构连接到衬底的垂直有源柱，电荷存储 垂直有源柱和栅电极之间的层，电荷存储层和垂直有源柱之间的隧道绝缘层，以及电荷存储层和栅电极之间的阻挡绝缘层。 电荷存储层包括分别与隔离绝缘层和隧道绝缘层相邻的第一和第二电荷存储层。 第一电荷存储层包括氮化硅层，第二电荷存储层包括氮氧化硅层。

公开(公告)号：US20120267701A1

公开(公告)日：2012-10-25

申请号：US13425584

申请日：2012-03-21

申请人： Soodoo Chae ,  Kihyun Hwang ,  Hanmei Choi ,  SeungHyun Lim

发明人： Soodoo Chae ,  Kihyun Hwang ,  Hanmei Choi ,  SeungHyun Lim

IPC分类号： H01L29/78

CPC分类号： H01L27/11582 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/1157

摘要： Nonvolatile memory devices include a vertical stack of nonvolatile memory cells. The vertical stack of nonvolatile memory cells includes a first nonvolatile memory cell having a first gate pattern therein, which is separated from a vertical active region by a first multi-layered dielectric pattern having a first thickness, and a second nonvolatile memory cell having a second gate pattern therein, which is separated from the vertical active region by a second multi-layered dielectric pattern having a second thickness. The second gate pattern is also separated from the first gate pattern by a distance less than a sum of the first and second thicknesses.

摘要翻译： 非易失性存储器件包括垂直堆叠的非易失性存储单元。 非易失性存储单元的垂直堆叠包括其中具有第一栅极图案的第一非易失性存储单元，其通过具有第一厚度的第一多层电介质图案与垂直有源区域分离，并且具有第二非易失性存储单元的第二非易失性存储单元 栅极图案，其通过具有第二厚度的第二多层电介质图案与垂直有源区域分离。 第二栅极图案也从第一栅极图案分离小于第一和第二厚度之和的距离。

公开(公告)号：US08987803B2

公开(公告)日：2015-03-24

申请号：US13425584

申请日：2012-03-21

申请人： Soodoo Chae ,  Kihyun Hwang ,  Hanmei Choi ,  SeungHyun Lim

发明人： Soodoo Chae ,  Kihyun Hwang ,  Hanmei Choi ,  SeungHyun Lim

IPC分类号： H01L29/78 ,  H01L27/115 ,  G11C5/02 ,  G11C16/04

CPC分类号： H01L27/11582 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/1157

摘要： Nonvolatile memory devices include a vertical stack of nonvolatile memory cells. The vertical stack of nonvolatile memory cells includes a first nonvolatile memory cell having a first gate pattern therein, which is separated from a vertical active region by a first multi-layered dielectric pattern having a first thickness, and a second nonvolatile memory cell having a second gate pattern therein, which is separated from the vertical active region by a second multi-layered dielectric pattern having a second thickness. The second gate pattern is also separated from the first gate pattern by a distance less than a sum of the first and second thicknesses.

摘要翻译： 非易失性存储器件包括垂直堆叠的非易失性存储单元。 非易失性存储单元的垂直堆叠包括其中具有第一栅极图案的第一非易失性存储单元，其通过具有第一厚度的第一多层电介质图案与垂直有源区域分离，并且具有第二非易失性存储单元的第二非易失性存储单元 栅极图案，其通过具有第二厚度的第二多层电介质图案与垂直有源区域分离。 第二栅极图案也与第一栅极图案分开小于第一和第二厚度之和的距离。

公开(公告)号：US20160225785A1

公开(公告)日：2016-08-04

申请号：US14960776

申请日：2015-12-07

申请人： Chaeho KIM ,  Sangryol Yang ,  Woong Lee ,  SeungHyun Lim

发明人： Chaeho KIM ,  Sangryol Yang ,  Woong Lee ,  SeungHyun Lim

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42348 ,  H01L29/513

摘要： A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.

摘要翻译： 一种半导体存储器件包括：堆叠，其包括交替重复堆叠在衬底上的栅电极和绝缘层。 细胞通道结构穿透堆叠。 单元沟道结构包括与基板接触的第一半导体图案和第一半导体图案上的第一沟道图案。 第一半导体图案延伸到从基板的表面到第一半导体图案的顶表面的第一高度。 衬底上的虚拟通道结构，与堆叠间隔开。 虚设通道结构包括接触衬底的第二半导体图案和第二半导体图案上的第二沟道图案。 第二半导体图案延伸到从基板的表面到第二半导体图案的顶表面的第二高度。 第一个高度大于第二个高度。

公开(公告)号：US09478561B2

公开(公告)日：2016-10-25

申请号：US14960776

申请日：2015-12-07

申请人： Chaeho Kim ,  Sangryol Yang ,  Woong Lee ,  SeungHyun Lim

发明人： Chaeho Kim ,  Sangryol Yang ,  Woong Lee ,  SeungHyun Lim

IPC分类号： H01L27/105 ,  H01L27/115 ,  H01L29/51 ,  H01L29/423

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42348 ,  H01L29/513

摘要： A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.

摘要翻译： 一种半导体存储器件包括：堆叠，其包括交替重复堆叠在衬底上的栅电极和绝缘层。 细胞通道结构穿透堆叠。 单元沟道结构包括与基板接触的第一半导体图案和第一半导体图案上的第一沟道图案。 第一半导体图案延伸到从基板的表面到第一半导体图案的顶表面的第一高度。 衬底上的虚拟通道结构，与堆叠间隔开。 虚设通道结构包括接触衬底的第二半导体图案和第二半导体图案上的第二沟道图案。 第二半导体图案延伸到从基板的表面到第二半导体图案的顶表面的第二高度。 第一个高度大于第二个高度。