公开(公告)号：US08987803B2

公开(公告)日：2015-03-24

申请号：US13425584

申请日：2012-03-21

申请人： Soodoo Chae ,  Kihyun Hwang ,  Hanmei Choi ,  SeungHyun Lim

发明人： Soodoo Chae ,  Kihyun Hwang ,  Hanmei Choi ,  SeungHyun Lim

IPC分类号： H01L29/78 ,  H01L27/115 ,  G11C5/02 ,  G11C16/04

CPC分类号： H01L27/11582 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/1157

摘要： Nonvolatile memory devices include a vertical stack of nonvolatile memory cells. The vertical stack of nonvolatile memory cells includes a first nonvolatile memory cell having a first gate pattern therein, which is separated from a vertical active region by a first multi-layered dielectric pattern having a first thickness, and a second nonvolatile memory cell having a second gate pattern therein, which is separated from the vertical active region by a second multi-layered dielectric pattern having a second thickness. The second gate pattern is also separated from the first gate pattern by a distance less than a sum of the first and second thicknesses.

摘要翻译： 非易失性存储器件包括垂直堆叠的非易失性存储单元。 非易失性存储单元的垂直堆叠包括其中具有第一栅极图案的第一非易失性存储单元，其通过具有第一厚度的第一多层电介质图案与垂直有源区域分离，并且具有第二非易失性存储单元的第二非易失性存储单元 栅极图案，其通过具有第二厚度的第二多层电介质图案与垂直有源区域分离。 第二栅极图案也与第一栅极图案分开小于第一和第二厚度之和的距离。

公开(公告)号：US20120267701A1

公开(公告)日：2012-10-25

申请号：US13425584

申请日：2012-03-21

申请人： Soodoo Chae ,  Kihyun Hwang ,  Hanmei Choi ,  SeungHyun Lim

发明人： Soodoo Chae ,  Kihyun Hwang ,  Hanmei Choi ,  SeungHyun Lim

IPC分类号： H01L29/78

CPC分类号： H01L27/11582 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/1157

摘要： Nonvolatile memory devices include a vertical stack of nonvolatile memory cells. The vertical stack of nonvolatile memory cells includes a first nonvolatile memory cell having a first gate pattern therein, which is separated from a vertical active region by a first multi-layered dielectric pattern having a first thickness, and a second nonvolatile memory cell having a second gate pattern therein, which is separated from the vertical active region by a second multi-layered dielectric pattern having a second thickness. The second gate pattern is also separated from the first gate pattern by a distance less than a sum of the first and second thicknesses.

摘要翻译： 非易失性存储器件包括垂直堆叠的非易失性存储单元。 非易失性存储单元的垂直堆叠包括其中具有第一栅极图案的第一非易失性存储单元，其通过具有第一厚度的第一多层电介质图案与垂直有源区域分离，并且具有第二非易失性存储单元的第二非易失性存储单元 栅极图案，其通过具有第二厚度的第二多层电介质图案与垂直有源区域分离。 第二栅极图案也从第一栅极图案分离小于第一和第二厚度之和的距离。

公开(公告)号：US20110303971A1

公开(公告)日：2011-12-15

申请号：US13157659

申请日：2011-06-10

申请人： Changwon Lee ,  Kihyun Hwang ,  Hanmei Choi ,  Sun Woo Lee ,  Junkyu Yang ,  Sunggil Kim ,  Jeonggil Lee ,  Seon-Ho Jo

发明人： Changwon Lee ,  Kihyun Hwang ,  Hanmei Choi ,  Sun Woo Lee ,  Junkyu Yang ,  Sunggil Kim ,  Jeonggil Lee ,  Seon-Ho Jo

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A method for manufacturing a three-dimensional semiconductor memory includes forming a plurality of stacked structures disposed on a substrate to be spaced apart from each other, each of the stacked structures including a plurality of dielectric patterns and a plurality of polysilicon patterns alternately stacked, forming a metal layer to cover sidewalls of the stacked structures and a top surface of the substrate exposed between the stacked structures, and forming stacked gate electrodes on the substrate and a conductive line in the substrate by performing a silicidation process between the metal layer and each of the polysilicon patterns and the substrate.

摘要翻译： 一种三维半导体存储器的制造方法，其特征在于，在基板上形成多个层叠结构，使其彼此间隔开，所述堆叠结构中的每一个包括多个电介质图案和多个多晶硅图案，交替层叠，形成 覆盖层叠结构的侧壁的金属层和露出在层叠结构之间的基板的顶面，通过在金属层与金属层之间进行硅化处理，在基板上形成层叠的栅电极和基板的导电线 多晶硅图案和衬底。

公开(公告)号：US08377817B2

公开(公告)日：2013-02-19

申请号：US13173304

申请日：2011-06-30

申请人： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

发明人： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

IPC分类号： H01L21/4763

CPC分类号： H01L29/788 ,  H01L23/5384 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

公开(公告)号：US09929179B2

公开(公告)日：2018-03-27

申请号：US15467311

申请日：2017-03-23

申请人： Yong-Hoon Son ,  Hanmei Choi ,  Kihyun Hwang

发明人： Yong-Hoon Son ,  Hanmei Choi ,  Kihyun Hwang

IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/66 ,  H01L27/11565 ,  H01L27/11575

CPC分类号： H04L5/0091 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926 ,  H04L1/1812

摘要： A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A plurality of active channel patterns can extend vertically from the substrate in a zig-zag pattern around a perimeter of the filling insulating pattern, where each of the active channel patterns having a respective non-circular shaped horizontal cross-section. A vertical stack of a plurality of gate lines can each extend horizontally around the filling insulating pattern and the plurality of active channel patterns.

公开(公告)号：US20110233648A1

公开(公告)日：2011-09-29

申请号：US13072078

申请日：2011-03-25

申请人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Dongchul Yoo ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

发明人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Dongchul Yoo ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

摘要翻译： 三维半导体存储器件及其制造方法。 三维半导体器件包括具有布置在衬底上的顺序层叠电极的电极结构，穿透电极结构的半导体图案，以及插入在半导体图案和电极结构之间的包括第一图案和第二图案的存储元件，第一 垂直延伸以横过电极的图案和第二图案水平延伸以跨越半导体图案。

公开(公告)号：US20170345907A1

公开(公告)日：2017-11-30

申请号：US15681050

申请日：2017-08-18

申请人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

发明人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC分类号： H01L29/423 ,  H01L29/792 ,  H01L29/51 ,  H01L27/06 ,  H01L27/11578 ,  H01L27/11556 ,  H01L27/11551 ,  H01L27/11582 ,  H01L21/3213

CPC分类号： H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US09536970B2

公开(公告)日：2017-01-03

申请号：US13072078

申请日：2011-03-25

申请人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Dongchul Yoo ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

发明人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Dongchul Yoo ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC分类号： H01L29/792 ,  H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H01L27/115 ,  H01L29/51

CPC分类号： H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US20150311301A1

公开(公告)日：2015-10-29

申请号：US14796569

申请日：2015-07-10

申请人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

发明人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC分类号： H01L29/423 ,  H01L27/115 ,  H01L29/51 ,  H01L29/792

CPC分类号： H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

摘要翻译： 三维半导体存储器件及其制造方法。 三维半导体器件包括具有布置在衬底上的顺序层叠电极的电极结构，穿透电极结构的半导体图案，以及插入在半导体图案和电极结构之间的包括第一图案和第二图案的存储元件，第一 垂直延伸以横过电极的图案和第二图案水平延伸以跨越半导体图案。

公开(公告)号：US20120001345A1

公开(公告)日：2012-01-05

申请号：US13173304

申请日：2011-06-30

申请人： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

发明人： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

IPC分类号： H01L23/48 ,  H01L21/306 ,  H01L21/768

CPC分类号： H01L29/788 ,  H01L23/5384 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

摘要翻译： 提供三维半导体器件。 该装置可以包括垂直和顺序堆叠的模具层，堆叠的模具层之间的导电图案，垂直穿过堆叠的模具层的插入图案，导电图案和插入图案之间的中间图案，以及模具层之间的保护层图案 和封堵图案，其中保护层图案由中间图案分离。