摘要:
An encoding/decoding apparatus and method for parallel correction of in-loop pixels based on complexity using a video parameter may include a complexity measuring unit to measure a complexity of an in-loop pixel correction process, using video codec parameter information, in a video codec, and a core allocating unit to evenly distribute jobs associated with the in-loop pixel correction process, using the measured complexity.
摘要:
An encoding/decoding apparatus and method for parallel correction of in-loop pixels based on complexity using a video parameter may include a complexity measuring unit to measure a complexity of an in-loop pixel correction process, using video codec parameter information, in a video codec, and a core allocating unit to evenly distribute jobs associated with the in-loop pixel correction process, using the measured complexity.
摘要:
A deblocking filtering apparatus and method based on raster scanning is provided. The deblocking filtering apparatus may include a boundary determining unit to determine whether at least one of a vertical edge boundary and a horizontal edge boundary of a block corresponds to at least one of a coding unit (CU) boundary, a transform unit (TU) boundary, and a prediction unit (PU) boundary, a boundary strength (BS) computing unit to compute a BS value for at least one of the vertical edge boundary and the horizontal edge boundary when at least one of the vertical edge boundary and the horizontal edge boundary of the block corresponds to at least one of the CU boundary, the TU boundary, and the PU boundary as a result of the determining, and a filtering performing unit to perform deblocking filtering on at least one of the vertical edge boundary and the horizontal edge boundary.
摘要:
An apparatus and method sequentially parses bitstreams based on a removal of an Emulation Prevention Byte (EPB). The apparatus and method may detect an EPB pattern from among sequentially input bitstreams, may store the bitstreams, may store a processed bitstream where the EPB pattern is removed, among the bitstreams, and may select an output of a register buffer based on an input of a buffer selection flag.
摘要:
Provided is an apparatus and method of dynamically distributing load occurring in multiple cores that may determine a corresponding core to perform functions constituting an application program, thereby enhancing the entire processing rate.
摘要:
Provided is an apparatus and method of dynamically distributing load occurring in multiple cores that may determine a corresponding core to perform functions constituting an application program, thereby enhancing the entire processing rate.
摘要:
A decoding apparatus and method store at least one table including at least one code, receive at least one instruction signal, and extract a symbol value and a symbol length from the at least one table based on the at least one instruction signal. The decoding apparatus calculates a target suffix length that minimizes the size of a generated table and minimizes the size of a non-prefix length of the at least one code.
摘要:
An image data decoding apparatus and method are based on an availability of reference data. The image data decoding apparatus may include a core to process decoding of image data, and an availability determining device to receive, from the core, availability verification request information with respect to a reference area of a first frame included in the image data, to determine an availability with respect to the reference area based on the received availability verification request information, and to transmit, to the core, the determined availability. When the reference area is available, the core may process decoding of a second frame based on the reference area.
摘要:
A decoding apparatus and method store at least one table including at least one code, receive at least one instruction signal, and extract a symbol value and a symbol length from the at least one table based on the at least one instruction signal. The decoding apparatus calculates a target suffix length that minimizes the size of a generated table and minimizes the size of a non-prefix length of the at least one code.
摘要:
A memory access address translating apparatus and method may each classify pixels included in an input image into a plurality of tiles, and may generate a new memory for each of the successive tiles to enable the successive tiles, among a plurality of tiles, to be stored in different banks.