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    Semiconductor memory devices including offset bit lines
    2.
    发明授权
    Semiconductor memory devices including offset bit lines 有权
    包括偏移位线的半导体存储器件

    公开(公告)号：US08013374B2

    公开(公告)日：2011-09-06

    申请号：US12465202

    申请日：2009-05-13

    申请人： Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    发明人： Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10814 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/11502

    摘要： A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.

    摘要翻译： 半导体存储器件可以包括具有多个有源区的衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。 长度可以大于宽度，并且多个有源区可以在第二轴的方向上设置在多个有效区列中。 可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。 衬底上的多个位线可以跨过多个字线对，每个位线电耦合到每个列的有源区的相应漏极部分，并且每个位线布置在相应的漏极部分和另一个漏极部分的另一个漏极部分之间 相同列的相邻有效区域。

    Semiconductor memory devices including offset active regions
    3.
    发明授权
    Semiconductor memory devices including offset active regions 有权
    包括偏移活动区域的半导体存储器件

    公开(公告)号：US07547936B2

    公开(公告)日：2009-06-16

    申请号：US11246594

    申请日：2005-10-06

    申请人： Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    发明人： Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    IPC分类号： H01L271/108

    CPC分类号： H01L27/11502 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855

    摘要： A semiconductor memory device may include a substrate having a plurality of active regions and a field isolation layer on the substrate surrounding the active regions of the substrate. Each of the plurality of active regions may have a length in a direction of a first axis and a width in a direction of a second axis, and the length may be greater than the width. The plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis, and active regions of adjacent columns may be offset in the direction of the second axis.

    摘要翻译： 半导体存储器件可以包括具有多个有源区的衬底和围绕衬底的有源区的衬底上的场隔离层。 多个有源区域中的每一个可以具有在第一轴线的方向上的长度和在第二轴线的方向上的宽度，并且该长度可以大于宽度。 多个有源区域可以沿着第二轴线的方向设置在多个活性区域列中，并且相邻列的有效区域可以在第二轴线的方向上偏移。

    Semiconductor Memory Devices Including Offset Bit Lines
    4.
    发明申请
    Semiconductor Memory Devices Including Offset Bit Lines 有权
    包括偏移位线的半导体存储器件

    公开(公告)号：US20090218609A1

    公开(公告)日：2009-09-03

    申请号：US12465202

    申请日：2009-05-13

    申请人： Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    发明人： Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10814 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/11502

    摘要： A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.

    摘要翻译： 半导体存储器件可以包括具有多个有源区的衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。 长度可以大于宽度，并且多个有源区可以在第二轴的方向上设置在多个有效区列中。 可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。 衬底上的多个位线可以跨过多个字线对，每个位线电耦合到每个列的有源区的相应漏极部分，并且每个位线布置在相应的漏极部分和另一个漏极部分的另一个漏极部分之间 相同列的相邻有效区域。

    Semiconductor Memory Devices Including Extended Memory Elements
    5.
    发明申请
    Semiconductor Memory Devices Including Extended Memory Elements 审中-公开
    包括扩展内存元素的半导体存储器件

    公开(公告)号：US20090218654A1

    公开(公告)日：2009-09-03

    申请号：US12465261

    申请日：2009-05-13

    申请人： Don-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    发明人： Don-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    IPC分类号： H01L29/06 ,  H01L29/68

    CPC分类号： H01L27/10814 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/11502

    摘要： A semiconductor memory device may include a semiconductor substrate having an active region thereof, and the active region may have a length and a width, with the length being greater than the width. A field isolation layer may be on the semiconductor substrate surrounding the active region. First and second wordlines may be on the substrate crossing the active region, with the first and second wordlines defining a drain portion of the active region between the first and second wordlines and first and second source portions of the active region at opposite ends of the active region. First and second memory storage elements may be respectively coupled to the first and second source portions of the active region, with the first and second wordlines being between portions of the respective first and second memory storage elements and the active region in a direction perpendicular to a surface of the substrate.

    摘要翻译： 半导体存储器件可以包括具有其有源区的半导体衬底，并且有源区可以具有长度和宽度，其长度大于宽度。 场隔离层可以在围绕有源区的半导体衬底上。 第一和第二字线可以在与有源区交叉的衬底上，其中第一和第二字线限定在第一和第二字线之间的有源区的漏极部分和有源区的第一和第二源极部分在有源区域的相对端处 地区。 第一和第二存储器存储元件可以分别耦合到有源区域的第一和第二源极部分，其中第一和第二字线在相应的第一和第二存储器存储元件的部分之间，并且有源区域在垂直于 基板的表面。

    Semiconductor Memory Devices Including Diagonal Bit Lines
    6.
    发明申请
    Semiconductor Memory Devices Including Diagonal Bit Lines 有权
    包括对角位线的半导体存储器件

    公开(公告)号：US20090218610A1

    公开(公告)日：2009-09-03

    申请号：US12465234

    申请日：2009-05-13

    申请人： Don-Hoon Goo ,  Han-Ku Cho ,  Joo-Tac Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    发明人： Don-Hoon Goo ,  Han-Ku Cho ,  Joo-Tac Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10814 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/11502

    摘要： A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a drain portion of a respective active region of each column, and with each bitline crossing drain portions of active regions of adjacent columns in different directions so that different portions of a same bitline are aligned in different directions on different active regions of adjacent columns.

    摘要翻译： 半导体存储器件可以包括具有多个有源区的半导体衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。 长度可以大于宽度，并且多个有源区域可以在第二轴线的方向上以多个列设置。 可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。 衬底上的多个位线可以跨越多个字线对，每个位线电耦合到每列的相应有源区的漏极部分，并且每个位线在不同方向上与相邻列的有源区域的漏极部分交叉 使得相同位线的不同部分在相邻列的不同有效区域上在不同方向上对准。

    Semiconductor memory devices including diagonal bit lines
    7.
    发明授权
    Semiconductor memory devices including diagonal bit lines 有权
    半导体存储器件包括对角位线

    公开(公告)号：US08013375B2

    公开(公告)日：2011-09-06

    申请号：US12465234

    申请日：2009-05-13

    申请人： Duo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tac Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    发明人： Duo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tac Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10814 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/11502

    摘要： A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a drain portion of a respective active region of each column, and with each bitline crossing drain portions of active regions of adjacent columns in different directions so that different portions of a same bitline are aligned in different directions on different active regions of adjacent columns.

    摘要翻译： 半导体存储器件可以包括具有多个有源区的半导体衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。 长度可以大于宽度，并且多个有源区域可以在第二轴线的方向上以多个列设置。 可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。 衬底上的多个位线可以跨越多个字线对，每个位线电耦合到每列的相应有源区的漏极部分，并且每个位线在不同方向上与相邻列的有源区域的漏极部分交叉 使得相同位线的不同部分在相邻列的不同有效区域上在不同方向上对准。

    Cell structure for a semiconductor memory device and method of fabricating the same
    8.
    发明申请
    Cell structure for a semiconductor memory device and method of fabricating the same 失效
    半导体存储器件的单元结构及其制造方法

    公开(公告)号：US20100096681A1

    公开(公告)日：2010-04-22

    申请号：US12654255

    申请日：2009-12-15

    申请人： Kyoung-Yun Baek ,  Yong-Sun Ko ,  Hak Kim ,  Yong-Kug Bae

    发明人： Kyoung-Yun Baek ,  Yong-Sun Ko ,  Hak Kim ,  Yong-Kug Bae

    IPC分类号： H01L27/108

    CPC分类号： H01L27/0207 ,  H01L27/10888

    摘要： In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.

    摘要翻译： 在存储器件的6F2单元结构及其制造方法中，多个有源区可以在两端部具有第一区域，在中心部分可以具有第二区域。 位线接触焊盘的一部分可以位于第二区域上，另一部分可以位于基板的不与多个有源区域重叠的第三区域上。 位线可以与第三区域的位线接触焊盘连接。 尽管6F2结构的单元电池，电池结构也可以更容易地形成。 多个有源区域可以具有包括主轴和短轴的椭圆形状。 多个有源区域可以被定位在长轴方向上，从而形成有源行，并且可以以这样的结构定位在短轴方向上，使得多个有源区域的中心与相邻的活动区域的中心 相邻活动行中的区域。

    Photoresist pattern, method of fabricating the same, and method of assuring the quality thereof
    9.
    发明申请
    Photoresist pattern, method of fabricating the same, and method of assuring the quality thereof 审中-公开
    光刻胶图案，其制造方法以及确保其质量的方法

    公开(公告)号：US20060105476A1

    公开(公告)日：2006-05-18

    申请号：US11319605

    申请日：2005-12-29

    申请人： Yeon-Dong Choi ,  Kyoung-Yun Baek

    发明人： Yeon-Dong Choi ,  Kyoung-Yun Baek

    IPC分类号： H01L21/66

    CPC分类号： H01L22/34 ,  G03F1/44 ,  G03F7/70625 ,  G03F7/7065 ,  Y10S438/942

    摘要： A photoresist pattern and a method of fabricating the same make it easy to quickly identify a particular portion of a photolithography process that is responsible for causing process defects. The method of fabricating the photoresist pattern includes forming main patterns having a predetermined critical dimension in device-forming regions of a semiconductor substrate, and forming a plurality of test patterns in scribe regions of the substrate. The scribe regions are defined alongside the device-forming regions and separate the device-forming regions from one another. The test patterns have shapes similar to that of the main patterns. Also, one of the test patterns has a critical dimensions similar to that of the main patterns, and other test patterns have respective critical dimensions that are different from the critical dimension of the main patterns.

    摘要翻译： 光致抗蚀剂图案及其制造方法使得易于识别导致工艺缺陷的光刻工艺的特定部分变得容易。 制造光致抗蚀剂图案的方法包括在半导体衬底的器件形成区域中形成具有预定临界尺寸的主图案，并在衬底的划线区域中形成多个测试图案。 划线区域沿着器件形成区域定义并且将器件形成区域彼此分离。 测试图案具有与主图案类似的形状。 此外，其中一个测试图案具有与主图案相似的关键尺寸，其他测试图案具有与主图案的临界尺寸不同的各自的关键尺寸。

    Cell structure for a semiconductor memory device and method of fabricating the same
    10.
    发明授权
    Cell structure for a semiconductor memory device and method of fabricating the same 失效
    半导体存储器件的单元结构及其制造方法

    公开(公告)号：US08084801B2

    公开(公告)日：2011-12-27

    申请号：US12654255

    申请日：2009-12-15

    申请人： Kyoung-Yun Baek ,  Yong-Sun Ko ,  Hak Kim ,  Yong-Kug Bae

    发明人： Kyoung-Yun Baek ,  Yong-Sun Ko ,  Hak Kim ,  Yong-Kug Bae

    IPC分类号： H01L21/336

    CPC分类号： H01L27/0207 ,  H01L27/10888

    摘要： In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.

    摘要翻译： 在存储器件的6F2单元结构及其制造方法中，多个有源区可以在两端部具有第一区域，在中心部分可以具有第二区域。 位线接触焊盘的一部分可以位于第二区域上，另一部分可以位于基板的不与多个有源区域重叠的第三区域上。 位线可以与第三区域的位线接触焊盘连接。 尽管6F2结构的单元电池，电池结构也可以更容易地形成。 多个有源区域可以具有包括主轴和短轴的椭圆形状。 多个有源区域可以被定位在长轴方向上，从而形成有源行，并且可以以这样的结构定位在短轴方向上，使得多个有源区域的中心与相邻的活动区域的中心 相邻活动行中的区域。