公开(公告)号：US08415189B2

公开(公告)日：2013-04-09

申请号：US12512779

申请日：2009-07-30

申请人： Doowon Kwon ,  Seung-Hun Shin

发明人： Doowon Kwon ,  Seung-Hun Shin

IPC分类号： H01L21/00

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14689

摘要： Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation region walls, wherein at least some of the logic isolation region walls are free of the impurity layer. The impurity layer and/or the less sloped logic isolation region walls may also be provided for NMOS devices in the logic region but not for PMOS devices in the logic region. Doped sacrificial layers may be used to fabricate the impurity layer.

摘要翻译： 图像传感器包括像素区域和逻辑区域。 像素区域中的像素隔离区域包括比逻辑区域中的逻辑隔离区域壁更少倾斜的像素隔离区域壁。 也可以在至少一些像素隔离区域壁附近提供杂质层，其中至少一些逻辑隔离区域壁不含杂质层。 也可以为逻辑区域中的NMOS器件提供杂质层和/或较小倾斜的逻辑隔离区域壁，但不提供给逻辑区域中的PMOS器件。 可以使用掺杂的牺牲层来制造杂质层。

公开(公告)号：US20100015747A1

公开(公告)日：2010-01-21

申请号：US12512779

申请日：2009-07-30

申请人： Doowon Kwon ,  Seung-Hun Shin

发明人： Doowon Kwon ,  Seung-Hun Shin

IPC分类号： H01L31/18

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14689

摘要： Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation region walls, wherein at least some of the logic isolation region walls are free of the impurity layer. The impurity layer and/or the less sloped logic isolation region walls may also be provided for NMOS devices in the logic region but not for PMOS devices in the logic region. Doped sacrificial layers may be used to fabricate the impurity layer.

摘要翻译： 图像传感器包括像素区域和逻辑区域。 像素区域中的像素隔离区域包括比逻辑区域中的逻辑隔离区域壁更少倾斜的像素隔离区域壁。 也可以在至少一些像素隔离区域壁附近提供杂质层，其中至少一些逻辑隔离区域壁不含杂质层。 也可以为逻辑区域中的NMOS器件提供杂质层和/或较小倾斜的逻辑隔离区域壁，但不提供给逻辑区域中的PMOS器件。 可以使用掺杂的牺牲层来制造杂质层。

公开(公告)号：US20080035963A1

公开(公告)日：2008-02-14

申请号：US11668016

申请日：2007-01-29

申请人： Doowon Kwon ,  Seung-Hun Shin

发明人： Doowon Kwon ,  Seung-Hun Shin

IPC分类号： H01L31/113

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14689

摘要： Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation region walls, wherein at least some of the logic isolation region walls are free of the impurity layer. The impurity layer and/or the less sloped logic isolation region walls may also be provided for NMOS devices in the logic region but not for PMOS devices in the logic region. Doped sacrificial layers may be used to fabricate the impurity layer.

摘要翻译： 图像传感器包括像素区域和逻辑区域。 像素区域中的像素隔离区域包括比逻辑区域中的逻辑隔离区域壁更少倾斜的像素隔离区域壁。 也可以在至少一些像素隔离区域壁附近提供杂质层，其中至少一些逻辑隔离区域壁不含杂质层。 也可以为逻辑区域中的NMOS器件提供杂质层和/或较小倾斜的逻辑隔离区域壁，但不提供给逻辑区域中的PMOS器件。 可以使用掺杂的牺牲层来制造杂质层。

公开(公告)号：US07586170B2

公开(公告)日：2009-09-08

申请号：US11668016

申请日：2007-01-29

申请人： Doowon Kwon ,  Seung-Hun Shin

发明人： Doowon Kwon ,  Seung-Hun Shin

IPC分类号： H01L31/00 ,  H01L31/062

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14689

摘要： Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation region walls, wherein at least some of the logic isolation region walls are free of the impurity layer. The impurity layer and/or the less sloped logic isolation region walls may also be provided for NMOS devices in the logic region but not for PMOS devices in the logic region. Doped sacrificial layers may be used to fabricate the impurity layer.

摘要翻译： 图像传感器包括像素区域和逻辑区域。 像素区域中的像素隔离区域包括比逻辑区域中的逻辑隔离区域壁更少倾斜的像素隔离区域壁。 也可以在至少一些像素隔离区域壁附近提供杂质层，其中至少一些逻辑隔离区域壁不含杂质层。 也可以为逻辑区域中的NMOS器件提供杂质层和/或较小倾斜的逻辑隔离区域壁，但不提供给逻辑区域中的PMOS器件。 可以使用掺杂的牺牲层来制造杂质层。

公开(公告)号：US20150263060A1

公开(公告)日：2015-09-17

申请号：US14726935

申请日：2015-06-01

申请人： Byung-Jun PARK ,  Seung-Hun Shin

发明人： Byung-Jun PARK ,  Seung-Hun Shin

IPC分类号： H01L27/146

CPC分类号： H01L27/14645 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14689 ,  H01L31/022408 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of manufacturing an integrated circuit device including a through via structure are provided. The methods may include forming an isolation trench through a substrate to form an inner substrate, which is enclosed by the isolation trench and forming an insulating layer in the isolation trench and on a surface of the substrate. The methods may also include forming a hole, which is spaced apart from the isolation trench and passes through a portion of the insulating layer formed on the surface of the substrate and the inner substrate and forming a conductive layer in the hole and on the insulating layer formed on the surface of the substrate. The methods may be used to manufacture image sensors.

摘要翻译： 提供了包括通孔结构的集成电路器件的制造方法。 所述方法可以包括通过衬底形成隔离沟槽，以形成内部衬底，其被隔离沟槽包围，并在隔离沟槽中和衬底的表面上形成绝缘层。 所述方法还可以包括形成与隔离沟槽间隔开的孔，并穿过形成在衬底表面和内衬底上的绝缘层的一部分，并在孔中和绝缘层上形成导电层 形成在基板的表面上。 该方法可用于制造图像传感器。

公开(公告)号：US20130323875A1

公开(公告)日：2013-12-05

申请号：US13803821

申请日：2013-03-14

申请人： Byung-Jun Park ,  Seung-Hun Shin

发明人： Byung-Jun Park ,  Seung-Hun Shin

IPC分类号： H01L31/0224 ,  H01L21/768

CPC分类号： H01L27/14645 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14689 ,  H01L31/022408 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of manufacturing an integrated circuit device including a through via structure are provided. The methods may include forming an isolation trench through a substrate to form an inner substrate, which is enclosed by the isolation trench and forming an insulating layer in the isolation trench and on a surface of the substrate. The methods may also include forming a hole, which is spaced apart from the isolation trench and passes through a portion of the insulating layer formed on the surface of the substrate and the inner substrate and forming a conductive layer in the hole and on the insulating layer formed on the surface of the substrate. The methods may be used to manufacture image sensors.

公开(公告)号：US09048354B2

公开(公告)日：2015-06-02

申请号：US13803821

申请日：2013-03-14

申请人： Byung-Jun Park ,  Seung-Hun Shin

发明人： Byung-Jun Park ,  Seung-Hun Shin

IPC分类号： H01L21/00 ,  H01L31/0224 ,  H01L21/768 ,  H01L27/146 ,  H01L23/48

CPC分类号： H01L27/14645 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14689 ,  H01L31/022408 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of manufacturing an integrated circuit device including a through via structure are provided. The methods may include forming an isolation trench through a substrate to form an inner substrate, which is enclosed by the isolation trench and forming an insulating layer in the isolation trench and on a surface of the substrate. The methods may also include forming a hole, which is spaced apart from the isolation trench and passes through a portion of the insulating layer formed on the surface of the substrate and the inner substrate and forming a conductive layer in the hole and on the insulating layer formed on the surface of the substrate. The methods may be used to manufacture image sensors.

摘要翻译： 提供了包括通孔结构的集成电路器件的制造方法。 所述方法可以包括通过衬底形成隔离沟槽以形成内部衬底，其被隔离沟槽包围并在隔离沟槽中和衬底的表面上形成绝缘层。 所述方法还可以包括形成与隔离沟槽间隔开的孔，并穿过形成在衬底表面和内衬底上的绝缘层的一部分，并在孔中和绝缘层上形成导电层 形成在基板的表面上。 该方法可用于制造图像传感器。

公开(公告)号：US07998782B2

公开(公告)日：2011-08-16

申请号：US12454818

申请日：2009-05-22

申请人： Jin-Ho Kim ,  Chang-Rok Moon ,  Seung-Hun Shin

发明人： Jin-Ho Kim ,  Chang-Rok Moon ,  Seung-Hun Shin

IPC分类号： H01L21/8238

CPC分类号： H01L27/14689 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14641

摘要： For fabricating an image sensor, an isolation structure is formed to define a first active region of a semiconductor substrate. A first transistor and a second transistor of a unit pixel are formed in the first active region. In addition, a threshold voltage lowering region is formed in a portion of the semiconductor substrate near a portion of the isolation structure abutting the second transistor in the first active region. The threshold voltage lowering region causes the second transistor to have a respective threshold voltage magnitude that is lower than for the first transistor. The threshold voltage lowering region is formed simultaneously with a passivation region in a second active region having a photodiode formed therein.

摘要翻译： 为了制造图像传感器，形成隔离结构以限定半导体衬底的第一有源区。 在第一有源区中形成单位像素的第一晶体管和第二晶体管。 此外，在靠近第一有源区域中的第二晶体管的隔离结构的一部分附近，在半导体衬底的一部分中形成阈值电压降低区域。 阈值电压降低区域使得第二晶体管具有比第一晶体管低的相应阈值电压幅值。 阈值电压降低区域与其中形成有光电二极管的第二有源区域中的钝化区域同时形成。

公开(公告)号：US20090317933A1

公开(公告)日：2009-12-24

申请号：US12457773

申请日：2009-06-22

申请人： Byung-Jun Park ,  Tae-Hun Lee ,  Seung-Hun Shin

发明人： Byung-Jun Park ,  Tae-Hun Lee ,  Seung-Hun Shin

IPC分类号： H01L31/0232

CPC分类号： H01L27/14683 ,  H01L27/1463 ,  H01L27/1464 ,  Y10S438/975

摘要： In a method of manufacturing a complementary metal-oxide semiconductor (CMOS) image sensor (CIS), an epitaxial layer may be formed on a first substrate including a chip area and a scribe lane area. A first impurity layer may be formed adjacent to the first substrate by implanting first impurities into the epitaxial layer. A photodiode may be formed in the epitaxial layer on the chip area. A circuit element electrically connected to the photodiode may be formed on the epitaxial layer. A protective layer protecting the circuit element may be formed on the epitaxial layer. A second substrate may be attached onto the protective layer. The first substrate may be removed to expose the epitaxial layer. A color filter layer may be formed on the exposed epitaxial layer using the first impurity layer as an alignment key. A microlens may be formed over the color filter layer.

摘要翻译： 在制造互补金属氧化物半导体（CMOS）图像传感器（CIS）的方法中，可以在包括芯片区域和划线区域的第一基板上形成外延层。 可以通过将第一杂质注入到外延层中而与第一衬底相邻地形成第一杂质层。 可以在芯片区域上的外延层中形成光电二极管。 电连接到光电二极管的电路元件可以形成在外延层上。 可以在外延层上形成保护电路元件的保护层。 第二基底可以附着在保护层上。 可以去除第一衬底以暴露外延层。 可以使用第一杂质层作为对准键，在暴露的外延层上形成滤色器层。 可以在滤色器层上形成微透镜。

公开(公告)号：US20120091515A1

公开(公告)日：2012-04-19

申请号：US13180898

申请日：2011-07-12

申请人： Gil-Sang Yoo ,  Chang-Rok Moon ,  Byung-Jun Park ,  Sang-Hoon Kim ,  Seung-Hun Shin

发明人： Gil-Sang Yoo ,  Chang-Rok Moon ,  Byung-Jun Park ,  Sang-Hoon Kim ,  Seung-Hun Shin

IPC分类号： H01L31/0224 ,  H01L23/48 ,  H01L31/0232

CPC分类号： H01L27/14636 ,  H01L27/14603 ,  H01L27/14618 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14689 ,  H01L2224/13 ,  H04N5/2253 ,  H04N5/2254

摘要： A semiconductor substrate includes a photodiode on a support substrate. An insulating layer is provided between the support substrate and the semiconductor substrate. A first conductive pattern is provided in the insulating layer. A first through electrode penetrates the support substrate to be in contact with the first conductive pattern.

摘要翻译： 半导体衬底包括在支撑衬底上的光电二极管。 在支撑基板和半导体基板之间设置绝缘层。 第一导电图案设置在绝缘层中。 第一穿透电极穿透支撑衬底以与第一导电图案接触。