公开(公告)号：US20070036020A1

公开(公告)日：2007-02-15

申请号：US11195082

申请日：2005-08-01

申请人： Edward Lee ,  Arvind Bomdica ,  Lin Chen ,  Claude Gauthier ,  Sam Huynh ,  Hiok-Tiaq Ng ,  John Ling ,  Jennifer Ho ,  Siji M.K. ,  Gin Yee ,  Joseph Macri

发明人： Edward Lee ,  Arvind Bomdica ,  Lin Chen ,  Claude Gauthier ,  Sam Huynh ,  Hiok-Tiaq Ng ,  John Ling ,  Jennifer Ho ,  Siji M.K. ,  Gin Yee ,  Joseph Macri

IPC分类号： G11C8/00

CPC分类号： H03L7/0814 ,  H03L7/07 ,  H03L7/0805 ,  H04L7/0004 ,  H04L7/0037 ,  H04L7/0337

摘要： An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.

摘要翻译： 描述了用于位移校正的IO方法和系统。 实施例包括具有在其间传送数据的多个组件的计算机系统。 在一个实施例中，系统组件从发送组件接收正向选通信号和多个数据位信号。 接收组件包括可选择对准前向选通采样时钟以提高采样精度的正向选通时钟恢复电路。 接收组件还包括至少一个数据比特时钟恢复电路，可配置为对准数据比特采样时钟，以提高采样精度，并接收来自正向选通时钟恢复电路的信号，使得数据比特采样时钟跟踪 系统运行期间的正向选通采样时钟。

公开(公告)号：US07688925B2

公开(公告)日：2010-03-30

申请号：US11195082

申请日：2005-08-01

申请人： Edward Lee ,  Arvind Bomdica ,  Lin Chen ,  Claude Gauthier ,  Sam Huynh ,  Hiok-Tiaq Ng ,  John Ling ,  Jennifer Ho ,  Siji Menokki Kandiyil ,  Gin Yee ,  Joseph Macri

发明人： Edward Lee ,  Arvind Bomdica ,  Lin Chen ,  Claude Gauthier ,  Sam Huynh ,  Hiok-Tiaq Ng ,  John Ling ,  Jennifer Ho ,  Siji Menokki Kandiyil ,  Gin Yee ,  Joseph Macri

IPC分类号： H04L7/00

CPC分类号： H03L7/0814 ,  H03L7/07 ,  H03L7/0805 ,  H04L7/0004 ,  H04L7/0037 ,  H04L7/0337

摘要： An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.

摘要翻译： 描述了用于位移校正的IO方法和系统。 实施例包括具有在其间传送数据的多个组件的计算机系统。 在一个实施例中，系统组件从发送组件接收正向选通信号和多个数据位信号。 接收组件包括可选择对准前向选通采样时钟以提高采样精度的正向选通时钟恢复电路。 接收组件还包括至少一个数据比特时钟恢复电路，可配置为对准数据比特采样时钟，以提高采样精度，并接收来自正向选通时钟恢复电路的信号，使得数据比特采样时钟跟踪 系统运行期间的正向选通采样时钟。

公开(公告)号：US20050114061A1

公开(公告)日：2005-05-26

申请号：US10704843

申请日：2003-11-10

申请人： Claude Gauthier ,  Gin Yee

发明人： Claude Gauthier ,  Gin Yee

IPC分类号： G01K15/00

CPC分类号： G01K15/00

摘要： A temperature monitoring technique that eliminates the need for bipolar devices. In one embodiment of the present invention, a long-channel MOS transistor is configured in a diode connection to sense change in temperature. The diode drives a linear regulator and an oscillator. The oscillator in turn drives a counter, which counts pulses for a fixed period of time. The system clock on the chip is used as a temperature-independent frequency to generate a count. The temperature-dependent frequency is counted for a fixed number of system clock cycles. The present invention eliminates band gap circuitry currently used in most thermal sensing devices to provide a temperature-independent reference.

摘要翻译： 一种不需要双极型器件的温度监测技术。 在本发明的一个实施例中，长沟道MOS晶体管配置在二极管连接中以检测温度变化。 二极管驱动线性稳压器和振荡器。 振荡器又驱动一个计数器，计数脉冲一段固定的时间。 芯片上的系统时钟用作与温度无关的频率来产生计数。 在固定数量的系统时钟周期内对温度依赖频率进行计数。 本发明消除了目前在大多数热感测装置中使用的带隙电路，以提供与温度无关的参考。

公开(公告)号：US06882196B2

公开(公告)日：2005-04-19

申请号：US10198453

申请日：2002-07-18

申请人： Gin Yee ,  Sudhakar Bobba ,  Claude Gauthier ,  Dean Liu ,  Lynn Ooi ,  Pradeep Trivedi

发明人： Gin Yee ,  Sudhakar Bobba ,  Claude Gauthier ,  Dean Liu ,  Lynn Ooi ,  Pradeep Trivedi

IPC分类号： H03K3/017 ,  H03K5/00 ,  H03K5/156

CPC分类号： H03K5/1565 ,  H03K2005/00045

摘要： A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a flip-flop dependent on a bias signal and the input clock signal. When triggered, the flip-flop outputs a transition on the output clock signal, which, in turn, serves as an input to a duty cycle corrector that generates the bias signal dependent on the configuration of the duty cycle corrector. The duty cycle corrector may be configured to generate the bias signal so as to be able to operatively control the duty cycle of the output clock signal.

摘要翻译： 提供了使用输入时钟信号来产生具有期望频率的输出时钟信号的装置。 该器件使用电压控制延迟元件，其根据偏置信号和输入时钟信号将触发器输出复位信号。 当触发时，触发器输出输出时钟信号的转变，输出时钟信号又作为占空比校正器的输入，占空比校正器根据占空比校正器的配置产生偏置信号。 占空比校正器可以被配置为产生偏置信号，以便能够可操作地控制输出时钟信号的占空比。

公开(公告)号：US20050168255A1

公开(公告)日：2005-08-04

申请号：US10771989

申请日：2004-02-04

申请人： Claude Gauthier ,  Pradeep Trivedi ,  Raymond Heald ,  Gin Yee

发明人： Claude Gauthier ,  Pradeep Trivedi ,  Raymond Heald ,  Gin Yee

IPC分类号： G01R31/317 ,  H03B1/00 ,  H03L7/081 ,  H03L7/089 ,  H03L7/18

CPC分类号： H03L7/18 ,  G01R31/31727 ,  G06F2217/76 ,  H03L7/0812 ,  H03L7/0893

摘要： A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the effects of aging. In an alternate embodiment, the power supply voltage control codes can be increased or decreased to compensate for aging effects. In another embodiment, a ring oscillator is used to approximate the effects of NBTI. In this embodiment, the frequency domain is converted to time domain using digital counters and programmable power supply control words are used to change the operating parameters of the power supply to compensate for aging effects.

摘要翻译： 一种用于补偿集成电路性能的年龄相关退化的方法和装置。 在一个实施例中，锁相环（PLL）电荷泵设置有多个支脚，其可以选择性地启用或禁用以补偿老化的影响。 在替代实施例中，可以增加或减少电源电压控制代码以补偿老化效应。 在另一个实施例中，环形振荡器用于近似NBTI的影响。 在本实施例中，使用数字计数器将频域转换为时域，并且使用可编程电源控制字来改变电源的操作参数以补偿老化效应。

公开(公告)号：US06976235B2

公开(公告)日：2005-12-13

申请号：US10246089

申请日：2002-09-18

申请人： Sudhakar Bobba ,  Gin Yee ,  Pradeep Trivedi

发明人： Sudhakar Bobba ,  Gin Yee ,  Pradeep Trivedi

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5036 ,  G06F2217/78

摘要： A method and apparatus for assigning a set of region-based voltage drop budgets to an integrated circuit is provided. Further, a method for partitioning an integrated circuit into optimal voltage drop regions includes analyzing the integrated circuit for worst-case voltage drop data. The worst-case voltage drop data is used to partition the integrated circuit into a set of voltage drop regions, wherein each voltage drop region is assigned a region-based voltage drop budget. The region-based voltage drop budget assigned to a particular voltage drop region is based on a worst-case voltage drop experienced by that voltage drop region.

摘要翻译： 提供了一种用于将一组基于区域的电压降预算分配给集成电路的方法和装置。 此外，用于将集成电路划分成最佳压降区域的方法包括分析集成电路以获得最坏情况的电压降数据。 最坏情况的电压降数据用于将集成电路分成一组电压降区域，其中每个电压降区域被分配有基于区域的电压降预算。 分配给特定电压降区域的基于区域的电压降预算是基于该压降区域经历的最坏情况的电压降。

公开(公告)号：US06549038B1

公开(公告)日：2003-04-15

申请号：US09662101

申请日：2000-09-14

申请人： Carl Sechen ,  Larry McMurchie ,  Tyler Thorp ,  Gin Yee

发明人： Carl Sechen ,  Larry McMurchie ,  Tyler Thorp ,  Gin Yee

IPC分类号： H03K1900

CPC分类号： H03K19/01728 ,  H03K19/0963

摘要： A method for improving the speed of conventional CMOS logic families is disclosed. When applied to static CMOS, OPL retains the restoring character of the logic family, including its high noise margins. Speedups of 2× to 3× over (optimized) conventional static CMOS are demonstrated for a variety of circuits, ranging from chains of gates, to datapath circuits, and to random logic benchmarks. Such speedups are obtained using identical netlists without remapping. When applied to pseudo-nMOS and dynamic families, in combination with remapping to wide-input NORs, OPL yields speedups of 4× to 5× over static CMOS. Since OPL applied to static CMOS is faster than conventional domino logic, and since it has higher noise margins than domino logic, we believe it will scale much better than domino with future processing technologies.

摘要翻译： 公开了一种用于提高传统CMOS逻辑系列的速度的方法。 当应用于静态CMOS时，OPL保留了逻辑系列的恢复特性，包括其高噪声容限。 针对从栅极链到数据路径电路和随机逻辑基准测试的各种电路，展示了2x至3x（优化的）常规静态CMOS的加速。 这种加速是使用相同的网表来获得的，而不重映射。 当应用于伪nMOS和动态族时，与重新映射到宽输入NOR相结合，OPL比静态CMOS产生4倍至5倍的加速。 由于OPL应用于静态CMOS比传统的多米诺逻辑更快，并且由于它具有比多米诺逻辑更高的噪声容限，我们相信它将比未来处理技术的多米诺骨牌更好。

公开(公告)号：US06707320B2

公开(公告)日：2004-03-16

申请号：US09997866

申请日：2001-11-30

申请人： Pradeep Trivedi ,  Gin Yee

发明人： Pradeep Trivedi ,  Gin Yee

IPC分类号： H03K519

CPC分类号： H03K5/19 ,  G06F1/04

摘要： A clock detect indicator capable of determining the presence of high and low frequency clock signals is provided. The clock detect indicator, which operates independent of a reference clock, has detection circuitry that determines whether a particular clock signal has alternating high-to-low and low-to-high transitions. Based on the determination, the clock detect indicator outputs a transition on a clock detect indication signal. Further, a method for detecting a clock signal in an integrated circuit is provided.

摘要翻译： 提供能够确定高频和低频时钟信号的存在的时钟检测指示器。 时钟检测指示器独立于参考时钟运行，具有检测电路，其确定特定时钟信号是否具有交替的高到低和低到高的转换。 基于该确定，时钟检测指示符在时钟检测指示信号上输出转换。 此外，提供了一种用于检测集成电路中的时钟信号的方法。

公开(公告)号：US06642756B1

公开(公告)日：2003-11-04

申请号：US10202798

申请日：2002-07-25

申请人： Gin Yee ,  Sudhakar Bobba ,  Lynn Ooi ,  Pradeep Trivedi

发明人： Gin Yee ,  Sudhakar Bobba ,  Lynn Ooi ,  Pradeep Trivedi

IPC分类号： H03B1900

CPC分类号： G06F7/68 ,  H03K5/00006

摘要： A frequency multiplier design that uses a flip-flop to output (1) a first edge on an output clock signal upon receipt of a first transition of an input clock signal and (2) a second edge on the output clock signal before receipt of a second transition of the input clock signal is provided. The frequency multiplier design uses circuitry dependent on the output clock signal to reset the flip-flop after some delay but before the second transition of the input clock signal, wherein the resetting of the flip-flop causes the flip-flop to output the second edge on the output clock signal.

摘要翻译： 一种倍增器设计，其使用触发器在接收到输入时钟信号的第一转换时输出（1）输出时钟信号上的第一边沿，以及（2）在接收到输出时钟信号之前的输出时钟信号上的第二边沿 提供输入时钟信号的第二转换。 倍频器设计使用取决于输出时钟信号的电路，在一段延迟之后但在输入时钟信号的第二次转换之前复位触发器，其中触发器的复位使触发器输出第二边沿 对输出时钟信号。

公开(公告)号：US06971079B2

公开(公告)日：2005-11-29

申请号：US10245972

申请日：2002-09-18

申请人： Gin Yee ,  Pradeep Trivedi ,  Sudhakar Bobba

发明人： Gin Yee ,  Pradeep Trivedi ,  Sudhakar Bobba

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031

摘要： A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for performing timing analysis on an integrated circuit partitioned into voltage drop regions is provided. During the timing analysis, a set of logic paths segments in each voltage drop region is tested to ensure that the integrated circuit meets a set of predefined timing requirements. Logic path segments that reside in different voltage drop regions are tested using a supply voltage inputted by the respective voltage drop region.

摘要翻译： 提供了一种通过基于区域的电压降预算来提高集成电路的定时精度的方法和装置。 此外，提供了一种用于对分压成电压降区域的集成电路进行定时分析的方法。 在定时分析期间，测试每个压降区域中的一组逻辑路径段，以确保集成电路满足一组预定义的时序要求。 使用由各个电压降区域输入的电源电压来测试驻留在不同电压降区域中的逻辑路径段。