公开(公告)号：US06971079B2

公开(公告)日：2005-11-29

申请号：US10245972

申请日：2002-09-18

申请人： Gin Yee ,  Pradeep Trivedi ,  Sudhakar Bobba

发明人： Gin Yee ,  Pradeep Trivedi ,  Sudhakar Bobba

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031

摘要： A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for performing timing analysis on an integrated circuit partitioned into voltage drop regions is provided. During the timing analysis, a set of logic paths segments in each voltage drop region is tested to ensure that the integrated circuit meets a set of predefined timing requirements. Logic path segments that reside in different voltage drop regions are tested using a supply voltage inputted by the respective voltage drop region.

摘要翻译： 提供了一种通过基于区域的电压降预算来提高集成电路的定时精度的方法和装置。 此外，提供了一种用于对分压成电压降区域的集成电路进行定时分析的方法。 在定时分析期间，测试每个压降区域中的一组逻辑路径段，以确保集成电路满足一组预定义的时序要求。 使用由各个电压降区域输入的电源电压来测试驻留在不同电压降区域中的逻辑路径段。

公开(公告)号：US20050168255A1

公开(公告)日：2005-08-04

申请号：US10771989

申请日：2004-02-04

申请人： Claude Gauthier ,  Pradeep Trivedi ,  Raymond Heald ,  Gin Yee

发明人： Claude Gauthier ,  Pradeep Trivedi ,  Raymond Heald ,  Gin Yee

IPC分类号： G01R31/317 ,  H03B1/00 ,  H03L7/081 ,  H03L7/089 ,  H03L7/18

CPC分类号： H03L7/18 ,  G01R31/31727 ,  G06F2217/76 ,  H03L7/0812 ,  H03L7/0893

摘要： A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the effects of aging. In an alternate embodiment, the power supply voltage control codes can be increased or decreased to compensate for aging effects. In another embodiment, a ring oscillator is used to approximate the effects of NBTI. In this embodiment, the frequency domain is converted to time domain using digital counters and programmable power supply control words are used to change the operating parameters of the power supply to compensate for aging effects.

摘要翻译： 一种用于补偿集成电路性能的年龄相关退化的方法和装置。 在一个实施例中，锁相环（PLL）电荷泵设置有多个支脚，其可以选择性地启用或禁用以补偿老化的影响。 在替代实施例中，可以增加或减少电源电压控制代码以补偿老化效应。 在另一个实施例中，环形振荡器用于近似NBTI的影响。 在本实施例中，使用数字计数器将频域转换为时域，并且使用可编程电源控制字来改变电源的操作参数以补偿老化效应。

公开(公告)号：US06707320B2

公开(公告)日：2004-03-16

申请号：US09997866

申请日：2001-11-30

申请人： Pradeep Trivedi ,  Gin Yee

发明人： Pradeep Trivedi ,  Gin Yee

IPC分类号： H03K519

CPC分类号： H03K5/19 ,  G06F1/04

摘要： A clock detect indicator capable of determining the presence of high and low frequency clock signals is provided. The clock detect indicator, which operates independent of a reference clock, has detection circuitry that determines whether a particular clock signal has alternating high-to-low and low-to-high transitions. Based on the determination, the clock detect indicator outputs a transition on a clock detect indication signal. Further, a method for detecting a clock signal in an integrated circuit is provided.

摘要翻译： 提供能够确定高频和低频时钟信号的存在的时钟检测指示器。 时钟检测指示器独立于参考时钟运行，具有检测电路，其确定特定时钟信号是否具有交替的高到低和低到高的转换。 基于该确定，时钟检测指示符在时钟检测指示信号上输出转换。 此外，提供了一种用于检测集成电路中的时钟信号的方法。

公开(公告)号：US06642756B1

公开(公告)日：2003-11-04

申请号：US10202798

申请日：2002-07-25

申请人： Gin Yee ,  Sudhakar Bobba ,  Lynn Ooi ,  Pradeep Trivedi

发明人： Gin Yee ,  Sudhakar Bobba ,  Lynn Ooi ,  Pradeep Trivedi

IPC分类号： H03B1900

CPC分类号： G06F7/68 ,  H03K5/00006

摘要： A frequency multiplier design that uses a flip-flop to output (1) a first edge on an output clock signal upon receipt of a first transition of an input clock signal and (2) a second edge on the output clock signal before receipt of a second transition of the input clock signal is provided. The frequency multiplier design uses circuitry dependent on the output clock signal to reset the flip-flop after some delay but before the second transition of the input clock signal, wherein the resetting of the flip-flop causes the flip-flop to output the second edge on the output clock signal.

摘要翻译： 一种倍增器设计，其使用触发器在接收到输入时钟信号的第一转换时输出（1）输出时钟信号上的第一边沿，以及（2）在接收到输出时钟信号之前的输出时钟信号上的第二边沿 提供输入时钟信号的第二转换。 倍频器设计使用取决于输出时钟信号的电路，在一段延迟之后但在输入时钟信号的第二次转换之前复位触发器，其中触发器的复位使触发器输出第二边沿 对输出时钟信号。

公开(公告)号：US06976235B2

公开(公告)日：2005-12-13

申请号：US10246089

申请日：2002-09-18

申请人： Sudhakar Bobba ,  Gin Yee ,  Pradeep Trivedi

发明人： Sudhakar Bobba ,  Gin Yee ,  Pradeep Trivedi

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5036 ,  G06F2217/78

摘要： A method and apparatus for assigning a set of region-based voltage drop budgets to an integrated circuit is provided. Further, a method for partitioning an integrated circuit into optimal voltage drop regions includes analyzing the integrated circuit for worst-case voltage drop data. The worst-case voltage drop data is used to partition the integrated circuit into a set of voltage drop regions, wherein each voltage drop region is assigned a region-based voltage drop budget. The region-based voltage drop budget assigned to a particular voltage drop region is based on a worst-case voltage drop experienced by that voltage drop region.

摘要翻译： 提供了一种用于将一组基于区域的电压降预算分配给集成电路的方法和装置。 此外，用于将集成电路划分成最佳压降区域的方法包括分析集成电路以获得最坏情况的电压降数据。 最坏情况的电压降数据用于将集成电路分成一组电压降区域，其中每个电压降区域被分配有基于区域的电压降预算。 分配给特定电压降区域的基于区域的电压降预算是基于该压降区域经历的最坏情况的电压降。

公开(公告)号：US06882196B2

公开(公告)日：2005-04-19

申请号：US10198453

申请日：2002-07-18

申请人： Gin Yee ,  Sudhakar Bobba ,  Claude Gauthier ,  Dean Liu ,  Lynn Ooi ,  Pradeep Trivedi

发明人： Gin Yee ,  Sudhakar Bobba ,  Claude Gauthier ,  Dean Liu ,  Lynn Ooi ,  Pradeep Trivedi

IPC分类号： H03K3/017 ,  H03K5/00 ,  H03K5/156

CPC分类号： H03K5/1565 ,  H03K2005/00045

摘要： A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a flip-flop dependent on a bias signal and the input clock signal. When triggered, the flip-flop outputs a transition on the output clock signal, which, in turn, serves as an input to a duty cycle corrector that generates the bias signal dependent on the configuration of the duty cycle corrector. The duty cycle corrector may be configured to generate the bias signal so as to be able to operatively control the duty cycle of the output clock signal.

摘要翻译： 提供了使用输入时钟信号来产生具有期望频率的输出时钟信号的装置。 该器件使用电压控制延迟元件，其根据偏置信号和输入时钟信号将触发器输出复位信号。 当触发时，触发器输出输出时钟信号的转变，输出时钟信号又作为占空比校正器的输入，占空比校正器根据占空比校正器的配置产生偏置信号。 占空比校正器可以被配置为产生偏置信号，以便能够可操作地控制输出时钟信号的占空比。

公开(公告)号：US06859068B1

公开(公告)日：2005-02-22

申请号：US10637285

申请日：2003-08-08

申请人： Pradeep Trivedi ,  Priya Ananthanarayanan

发明人： Pradeep Trivedi ,  Priya Ananthanarayanan

IPC分类号： G11C7/10 ,  H03K5/135 ,  H03K19/003 ,  H03L7/00 ,  H03L7/081 ,  H03K19/094

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1093 ,  H03K5/135 ,  H03K19/00323 ,  H03L7/00 ,  H03L7/0812

摘要： A self-correcting I/O interface driver scheme uses a delay difference detector to detect a difference in delays between an I/O data path and an I/O clock path. The delay difference detector inputs signals from a data output pin connected to the I/O data path and a clock output pin connected to the I/O clock path. Upon determining a delay difference between the signals from the data and clock output pins, the delay difference detector generates signals to one or more drivers in the I/O data path and the I/O clock path. These signals from the delay difference detector are used to effectively adjust delays of the one or more drivers in order to effectively reduce the delay difference between the I/O data path and the I/O clock path.

摘要翻译： 自校正I / O接口驱动器方案使用延迟差检测器来检测I / O数据路径和I / O时钟路径之间的延迟差异。 延迟差检测器输入来自连接到I / O数据通路的数据输出引脚的信号和连接到I / O时钟通路的时钟输出引脚。 在确定来自数据和时钟输出引脚的信号之间的延迟差时，延迟差检测器向I / O数据通路和I / O时钟通路中的一个或多个驱动器产生信号。 来自延迟差检测器的这些信号用于有效地调整一个或多个驱动器的延迟，以便有效地减少I / O数据路径和I / O时钟路径之间的延迟差。

公开(公告)号：US06806698B2

公开(公告)日：2004-10-19

申请号：US10078945

申请日：2002-02-19

申请人： Claude Gauthier ,  Brian Amick ,  Spencer Gold ,  Dean Liu ,  Kamran Zarrineh ,  Pradeep Trivedi

发明人： Claude Gauthier ,  Brian Amick ,  Spencer Gold ,  Dean Liu ,  Kamran Zarrineh ,  Pradeep Trivedi

IPC分类号： G01R2314

CPC分类号： H03M1/0621 ,  G01K7/01 ,  G01K7/32 ,  H03M1/60

摘要： A method and apparatus that uses the difference between two nodal voltages, such as a temperature-independent voltage and a temperature-dependent voltage, to determine the actual temperature at a point on an integrated circuit is provided. Further, a method and apparatus that converts a difference between nodal voltages in an integrated circuit from an analog to a digital quantity on the integrated circuit such that the difference in voltage may be used by an on-chip digital system is provided. Further, a method and apparatus for quantifying a difference in voltage between a first node and a second node of a temperature sensor is provided.

摘要翻译： 提供了使用两个节点电压之间的差异的方法和装置，例如与温度无关的电压和与温度有关的电压，以确定集成电路上的点处的实际温度。 此外，提供了一种将集成电路中的节点电压与集成电路中的数字量之间的差异转换为使得片上数字系统可以使用电压差的方法和装置。 此外，提供了用于量化温度传感器的第一节点和第二节点之间的电压差的方法和装置。

公开(公告)号：US06753740B2

公开(公告)日：2004-06-22

申请号：US10147593

申请日：2002-05-17

申请人： Claude Gauthier ,  Brian W. Amick ,  Pradeep Trivedi ,  Dean Liu

发明人： Claude Gauthier ,  Brian W. Amick ,  Pradeep Trivedi ,  Dean Liu

IPC分类号： H03B100

CPC分类号： H03L7/0893 ,  H03L7/18

摘要： A calibration and adjustment system for post-fabrication control of a phase locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired phase locked loop performance characteristic after the phase locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the phase locked loop.

摘要翻译： 提供了一种用于锁相环偏置发生器的后制造控制的校准和调节系统。 校准和调整系统包括可操作地连接到偏置发生器的调节电路，其中调节电路是可控制的，以便于修正偏置发生器的电压输出。 由偏置发生器输出的电压的这种控制允许设计者在制造了锁相环之后实现期望的锁相环性能特性。 可以存储和随后读取偏置发生器输出中期望的调节量的代表值来调整锁相环。

公开(公告)号：US06704680B2

公开(公告)日：2004-03-09

申请号：US10075205

申请日：2002-02-14

申请人： Brian Amick ,  Claude Gauthier ,  Pradeep Trivedi ,  Dean Liu

发明人： Brian Amick ,  Claude Gauthier ,  Pradeep Trivedi ,  Dean Liu

IPC分类号： G05F302

CPC分类号： G06F17/5036 ,  G01K15/00 ,  G06F17/5063

摘要： A method for optimizing a decoupling capacitance for an on-chip temperature sensor is provided. A representative power supply waveform having noise is input into a simulation of the on-chip temperature sensor; a difference between a temperature representative input and a temperature dependent output of the on-chip temperature sensor is determined; and an amount of the decoupling capacitance is adjusted until the difference falls below a pre-selected value. A computer system for optimizing a decoupling capacitance for an on-chip temperature sensor is also provided. A computer-readable medium having recorded thereon instructions executable by a processor for optimizing a decoupling capacitance for an on-chip temperature sensor is further provided.

摘要翻译： 提供了一种用于优化片上温度传感器的去耦电容的方法。 将具有噪声的代表性电源波形输入到片上温度传感器的仿真中; 确定温度代表性输入和片上温度传感器的与温度相关的输出之间的差异; 并且调整去耦电容的量，直到差降低到预选值以下。 还提供了一种用于优化片上温度传感器的去耦电容的计算机系统。 还提供了一种其上记录有可由处理器执行以用于优化用于片上温度传感器的去耦电容的指令的计算机可读介质。