公开(公告)号：US20070154522A1

公开(公告)日：2007-07-05

申请号：US10585259

申请日：2004-08-04

申请人： Edwin Chow ,  Yi Yang

发明人： Edwin Chow ,  Yi Yang

IPC分类号： A61F2/02 ,  B01J13/02

CPC分类号： A61F9/0017 ,  A61K9/0051 ,  C08F2/22 ,  C08F220/14 ,  C08F220/28

摘要： A bicontinuous microemulsion of water, a monomer, and a surfactant copolymerizable with the monomer is polymerized to form a transparent and porous polymer defining interconnected pores. The pores may have a pore diameter in the range of 10 to 100 mm. The microemulsion may further include a drug such that, when the polymer is formed, the drug is dispersed in one or both of the polymer and the pores and is releasable therefrom when the polymer is in contact with a liquid. The drug may be an ophthalmic drug and the polyer can be used to form drug delivery devices, such as contact lenses and artificial corneas.

摘要翻译： 水，单体和可与单体共聚的表面活性剂的双连续微乳液被聚合以形成限定互连孔的透明和多孔聚合物。 孔的孔径可以在10〜100mm的范围内。 微乳液可以进一步包括药物，使得当形成聚合物时，药物分散在聚合物和孔中的一种或两种中，并且当聚合物与液体接触时可从其释放。 药物可以是眼科药物，并且聚合物可用于形成药物递送装置，例如隐形眼镜和人造角膜。

公开(公告)号：US5689459A

公开(公告)日：1997-11-18

申请号：US744559

申请日：1996-11-05

申请人： Shang-De Chang ,  Jia-Hwang Chang ,  Edwin Chow

发明人： Shang-De Chang ,  Jia-Hwang Chang ,  Edwin Chow

IPC分类号： G11C16/04 ,  G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC分类号： G11C16/345 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/7883

摘要： A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

公开(公告)号：US5615147A

公开(公告)日：1997-03-25

申请号：US534725

申请日：1995-09-27

申请人： Shang-De Chang ,  Jia-Hwang Chang ,  Edwin Chow

发明人： Shang-De Chang ,  Jia-Hwang Chang ,  Edwin Chow

IPC分类号： G11C16/04 ,  G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C13/00

CPC分类号： G11C16/345 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/7883

摘要： A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

摘要翻译： 能够使用Fowler-Nordheim隧道进行编程和擦除并能够使用低电压操作的单晶体管电可擦除可编程存储器件。 源极和漏极区域中的每一个的部分与第一栅极介电层重叠，并且选择互互电介质层以具有高的介电常数，以便最大化浮动栅极，控制栅极，源极和漏极之间的电容耦合比。 通过首先将单元格块升高到高电压阈值并单独降低所选单元格的电压阈值来设置阵列中单元格的逻辑状态。

公开(公告)号：US5940325A

公开(公告)日：1999-08-17

申请号：US971975

申请日：1997-11-17

申请人： Shang-De Chang ,  Jai-Hwang Chang ,  Edwin Chow

发明人： Shang-De Chang ,  Jai-Hwang Chang ,  Edwin Chow

IPC分类号： G11C16/04 ,  G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  H01L29/78

CPC分类号： G11C16/345 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/7883

摘要： A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

摘要翻译： 能够使用Fowler-Nordheim隧道进行编程和擦除并能够使用低电压操作的单晶体管电可擦除可编程存储器件。 源极和漏极区域中的每一个的部分与第一栅极介电层重叠，并且选择互互电介质层以具有高的介电常数，以便最大化浮动栅极，控制栅极，源极和漏极之间的电容耦合比。 通过首先将单元格块升高到高电压阈值并单独降低所选单元格的电压阈值来设置阵列中单元格的逻辑状态。

公开(公告)号：US5687120A

公开(公告)日：1997-11-11

申请号：US534700

申请日：1995-09-27

申请人： Shang-De Chang ,  Jia-Hwang Chang ,  Edwin Chow

发明人： Shang-De Chang ,  Jia-Hwang Chang ,  Edwin Chow

IPC分类号： G11C16/04 ,  G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C16/345 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/7883

摘要： A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

摘要翻译： 能够使用Fowler-Nordheim隧道进行编程和擦除并能够使用低电压操作的单晶体管电可擦除可编程存储器件。 源极和漏极区域中的每一个的部分与第一栅极介电层重叠，并且选择互互电介质层以具有高的介电常数，以便最大化浮动栅极，控制栅极，源极和漏极之间的电容耦合比。 通过首先将单元格块升高到高电压阈值并单独降低所选单元格的电压阈值来设置阵列中单元格的逻辑状态。

公开(公告)号：US5587947A

公开(公告)日：1996-12-24

申请号：US534691

申请日：1995-09-27

申请人： Shang-De Chang ,  Jia-Hwang Chang ,  Edwin Chow

发明人： Shang-De Chang ,  Jia-Hwang Chang ,  Edwin Chow

IPC分类号： G11C16/04 ,  G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/345 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/7883

摘要： A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

摘要翻译： 能够使用Fowler-Nordheim隧道进行编程和擦除并能够使用低电压操作的单晶体管电可擦除可编程存储器件。 源极和漏极区域中的每一个的部分与第一栅极介电层重叠，并且选择互互电介质层以具有高的介电常数，以便最大化浮动栅极，控制栅极，源极和漏极之间的电容耦合比。 通过首先将单元格块升高到高电压阈值并单独降低所选单元格的电压阈值来设置阵列中单元格的逻辑状态。