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    METHOD AND SYSTEM FOR PROVIDING SPIN TRANSFER TUNNELING MAGNETIC MEMORIES UTILIZING UNIDIRECTIONAL POLARITY SELECTION DEVICES
    5.
    发明申请
    METHOD AND SYSTEM FOR PROVIDING SPIN TRANSFER TUNNELING MAGNETIC MEMORIES UTILIZING UNIDIRECTIONAL POLARITY SELECTION DEVICES 审中-公开
    使用单向极性选择装置提供旋转传输磁性记忆体的方法和系统

    公开(公告)号：US20090185410A1

    公开(公告)日：2009-07-23

    申请号：US12017532

    申请日：2008-01-22

    申请人： Yiming Huai ,  Eugene Chen ,  Frank Albert ,  Jia-Hwang Chang

    发明人： Yiming Huai ,  Eugene Chen ,  Frank Albert ,  Jia-Hwang Chang

    IPC分类号： G11C11/02

    CPC分类号： G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    摘要： A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and a plurality of unidirectional polarity selection devices. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The unidirectional polarity selection devices are connected in parallel and such that they have opposing polarities. The magnetic memory may include a plurality of magnetic storage cells, a plurality of bit lines corresponding to the plurality of magnetic storage cells, and a plurality of source lines corresponding to the plurality of magnetic storage cells.

    摘要翻译： 描述了包含该单元的磁存储单元和磁存储器。 磁存储单元包括至少一个磁性元件和多个单向极性选择装置。 磁性元件可通过驱动通过磁性元件的写入电流来编程。 单向极性选择装置并联连接并且具有相反的极性。 磁存储器可以包括多个磁存储单元，对应于多个磁存储单元的多个位线，以及对应于多个磁存储单元的多个源极线。

    Testability architecture and techniques for programmable interconnect architecture
    6.
    发明授权
    Testability architecture and techniques for programmable interconnect architecture 失效
    可测试架构和可编程互连架构技术

    公开(公告)号：US5208530A

    公开(公告)日：1993-05-04

    申请号：US889838

    申请日：1992-05-26

    申请人： Khaled A. El-Ayat ,  Jia-Hwang Chang

    发明人： Khaled A. El-Ayat ,  Jia-Hwang Chang

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  H03K19/177

    CPC分类号： H03K19/17764 ,  G01R31/2884 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/1778

    摘要： Apparatus for performing high voltage testing of high-voltage transistors in the programming paths of a user-configurable integrated circuit including a plurality of conductors which may be connected to one another and to functional circuit blocks by programming user-programmable antifuse elements connected thereto to form electronic circuits, prior to formation of the electronic circuits by a user, including circuitry, responsive to signals provided to the integrated circuit from an external source, for temporarily connecting together a first group of the conductors to form a circuit path, the circuit path including the source and drain of at least one of the high-voltage transistors during a selected time period; circuitry for driving the circuit path and the gate of the at least one high-voltage transistor to a first voltage potential during the selected time period; circuitry for driving the bulk semiconductor region in the integrated circuit containing the source and drain of the at least one high-voltage transistor to a second voltage potential different from the first voltage potential during the selected time period, wherein the difference between the first voltage potential and the second voltage potential is more than the voltage necessary to cause degradation of faulty high-voltage transistors but less than the voltage necessary to cause degradation of properly functioning high-voltage transistors; and circuitry for measuring the current flowing between the first and second voltage potentials during the selected time period.

    摘要翻译： 用于在用户可配置的集成电路的编程路径中进行高压晶体管的高压测试的装置，包括可以通过编程连接到其上的与用户可编程的反熔丝元件相互连接的多个导体和功能电路块，以形成 电子电路，在用户形成电子电路之前，包括电路，响应于从外部源提供给集成电路的信号，用于将第一组导体临时连接在一起以形成电路路径，电路路径包括 在选定时间段内的至少一个高压晶体管的源极和漏极; 电路，用于在所选择的时间周期内将电路路径和所述至少一个高压晶体管的栅极驱动到第一电压电位; 电路，用于将所述集成电路中的所述体半导体区域驱动以将所述至少一个高压晶体管的源极和漏极驱动到在所选择的时间段内与所述第一电压电位不同的第二电压电位，其中所述第一电压电位 并且第二电压电位大于导致故障高压晶体管劣化所需的电压，但小于使正常工作的高压晶体管劣化所必需的电压; 以及用于在所选择的时间段内测量在第一和第二电压电位之间流动的电流的电路。

    Testability architecture and techniques for programmable interconnect architecture
    7.
    发明授权
    Testability architecture and techniques for programmable interconnect architecture 失效
    可测试架构和可编程互连架构技术

    公开(公告)号：US5432441A

    公开(公告)日：1995-07-11

    申请号：US102381

    申请日：1993-08-05

    申请人： Khaled A. El-Ayat ,  Jia-Hwang Chang

    发明人： Khaled A. El-Ayat ,  Jia-Hwang Chang

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  H03K19/177 ,  G01R31/02

    CPC分类号： H03K19/17764 ,  G01R31/2884 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17744

    摘要： In an integrated circuit having a plurality of function modules, each of the function modules having at least two inputs and at least one output. The integrated circuit is user programmable such that interconnections between selected ones of the function modules and input/output pins on the integrated circuit may be made. The integrated circuit further having two states, a first unprogrammed state where none of the interconnections have been made, and a second, programmed state in which selected interconnections have been made. Circuitry for testing the functionality of individual ones of the function modules when the integrated circuit is in the unprogrammed state comprises addressing means for selecting any one of the function modules, data input means for providing a selected logic level to at least one of the inputs of the function module selected by the addressing means, and output-connecting means, responsive to the addressing means, for temporarily connecting the output of the selected one of the function modules to one of the input/output pins on the integrated circuit.

    摘要翻译： 在具有多个功能模块的集成电路中，每个功能模块具有至少两个输入和至少一个输出。 集成电路是用户可编程的，使得可以制造集成电路上的功能模块中的选定功能模块和输入/输出引脚之间的互连。 集成电路还具有两个状态，即没有进行互连的第一未编程状态，以及已经进行了选择的互连的第二编程状态。 当集成电路处于未编程状态时用于测试各个功能模块的功能的电路包括用于选择任何一个功能模块的寻址装置，用于将所选逻辑电平提供给至少一个输入的数据输入装置 所述功能模块由所述寻址装置选择，以及输出连接装置，响应于所述寻址装置，将所选择的一个所述功能模块的输出临时连接到所述集成电路上的所述输入/输出引脚之一。

    Testability architecture and techniques for programmable interconnect architecture
    8.
    发明授权
    Testability architecture and techniques for programmable interconnect architecture 失效
    可测试架构和可编程互连架构技术

    公开(公告)号：US5083083A

    公开(公告)日：1992-01-21

    申请号：US375799

    申请日：1989-07-05

    申请人： Khaled A. El-Ayat ,  Jia-Hwang Chang

    发明人： Khaled A. El-Ayat ,  Jia-Hwang Chang

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  H03K19/177

    CPC分类号： H03K19/17764 ,  G01R31/2884 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/1778

    摘要： In a user-configurable integrated circuit including a plurality of uncommitted conductors which may be programmably connected to one another and to functional circuit blocks by a user to form electronic circuits, apparatus for testing for defects in the form of breaks in the electrical continuity of individual ones of the conductors prior to formation of the electronic circuits by a user, including circuitry responsive to external signals for temporarily connecting together selected ones of the uncommitted conductors to form a series circuit having a first end conductor and a second end conductor, circuitry for placing an electrical charge on the first end conductor such that a selected dynamic voltage is placed on the first end conductor, circuitry for driving the second end conductor to a voltage different from the selected dynamic voltage, circuitry for sensing the voltage on the first end conductor at a predetermined time after the driving voltage has been removed, circuitry for storing a signal related to the sensed voltage on the first end conductor, and circuitry for communicating the signal to an input/output pad of the integrated circuit.

    摘要翻译： 在用户可配置的集成电路中，包括可以可编程地彼此连接的多个未提交的导体和由用户形成电子电路的功能电路块，用于测试个体电连续性中的断裂形式的缺陷的装置 由用户形成电子电路之前的导​​体中的一个，包括响应于外部信号的电路，用于将未提交的导体临时连接在一起以形成具有第一端导体和第二端导体的串联电路，用于放置的电路 在第一端部导体上的电荷，使得选择的动态电压被放置在第一端部导体上，用于将第二端部导体驱动到与选择的动态电压不同的电压的电路，用于感测第一端部导体上的电压的电路 在驱动电压被去除之后的预定时间， 将与第一端部导体上的检测到的电压相关的信号，以及用于将该信号传送到集成电路的输入/输出焊盘的电路。

    Programmable and Redundant Circuitry Based On Magnetic Tunnel Junction (MTJ)
    10.
    发明申请
    Programmable and Redundant Circuitry Based On Magnetic Tunnel Junction (MTJ) 有权
    基于磁隧道结的可编程和冗余电路（MTJ）

    公开(公告)号：US20100067293A1

    公开(公告)日：2010-03-18

    申请号：US12210126

    申请日：2008-09-12

    申请人： David Chang-Cheng Yu ,  Xiao Luo ,  Jia-Hwang Chang

    发明人： David Chang-Cheng Yu ,  Xiao Luo ,  Jia-Hwang Chang

    IPC分类号： G11C11/02

    CPC分类号： G11C11/1675 ,  G11C11/161

    摘要： Techniques, apparatus and circuits based on magnetic or magnetoresistive tunnel junctions (MTJs). In one aspect, a programmable circuit device can include a magnetic tunnel junction (MTJ); a MTJ control circuit coupled to the MTJ to control the MTJ to cause a breakdown in the MTJ in programming the MTJ; and a sensing circuit coupled to the MTJ to sense a voltage under a breakdown condition of the MTJ.

    摘要翻译： 基于磁阻或磁阻隧道结（MTJ）的技术，装置和电路。 一方面，可编程电路装置可包括磁性隧道结（MTJ）; 耦合到MTJ的MTJ控制电路以控制MTJ在MTJ编程中引起MTJ中的故障; 以及耦合到MTJ以感测在MTJ的击穿情况下的电压的感测电路。