SEMICONDUCTOR TEST METHOD, SEMICONDUCTOR TEST APPARATUS, AND COMPUTER READABLE MEDIUM
    3.
    发明申请
    SEMICONDUCTOR TEST METHOD, SEMICONDUCTOR TEST APPARATUS, AND COMPUTER READABLE MEDIUM 审中-公开
    半导体测试方法,半导体测试仪器和计算机可读介质

    公开(公告)号:US20110055645A1

    公开(公告)日:2011-03-03

    申请号:US12873631

    申请日:2010-09-01

    IPC分类号: G11C29/08 G06F11/26

    摘要: A semiconductor test apparatus includes an inputting module, a monitor, a converter, a storage, and a tester. The inputting module inputs addresses for first test, in which the addresses of a plurality of semiconductor memories are arrayed in an arbitrary order. The monitor monitors test time of the first test on each semiconductor memory. The converter sorts the addresses of the semiconductor memories based on the test time in order to convert the address for the first test to addresses for a second test. The storage stores the addresses for the second test. The tester tests each semiconductor device based on the addresses for the second test stored in the storage.

    摘要翻译: 半导体测试装置包括输入模块,监视器,转换器,存储器和测试器。 输入模块输入用于第一测试的地址,其中多个半导体存储器的地址以任意顺序排列。 监视器监视每个半导体存储器上的第一次测试的测试时间。 转换器根据测试时间对半导体存储器的地址进行排序,以将第一测试的地址转换为第二测试的地址。 存储器存储第二次测试的地址。 测试仪基于存储在存储器中的第二测试的地址测试每个半导体器件。

    Testing apparatus for semiconductor device
    4.
    发明授权
    Testing apparatus for semiconductor device 失效
    半导体器件测试装置

    公开(公告)号:US5917833A

    公开(公告)日:1999-06-29

    申请号:US988471

    申请日:1997-12-10

    申请人: Tsunehiro Sato

    发明人: Tsunehiro Sato

    摘要: A testing apparatus for semiconductor device capable of preventing reduction in the number of devices to be simultaneously measured is provided. Address of a measurement section of a semiconductor device to be measured, input data inputted to the measurement section and expected data to be outputted from the semiconductor device when the input data is inputted are generated by an ALPG. Output data actually outputted from the semiconductor device when the input data is inputted and expected data are compared with each other at a comparison unit. Comparison result is outputted as fail information. By a test pass control unit, there is generated test pass information for selecting fail information on the basis of divisional test information inputted in the case where the cycle time of test is faster than the cycle time of the fail information storage memory. Memory cell within the fail information storage memory is selected on the basis of address of the measurement section. Thus, fail information is written into the selected memory cell on the basis of test pass information by a fail information write control unit.

    摘要翻译: 提供一种能够防止同时测量的设备的数量减少的半导体器件的测试装置。 通过ALPG生成要测量的半导体器件的测量部分的地址,输入到测量部分的输入数据和输入数据时从半导体器件输出的期望数据。 当输入数据被输入时,实际从半导体器件输出的输出数据和预期数据在比较单元中相互比较。 比较结果作为失败信息输出。 通过测试通过控制单元,生成用于根据在测试的周期时间比故障信息存储存储器的周期时间快的情况下输入的分割测试信息来选择失败信息的测试通过信息。 基于测量部分的地址选择故障信息存储存储器内的存储单元。 因此,故障信息写入控制单元基于测试通过信息将故障信息写入所选存储单元。