公开(公告)号：US20150236169A1

公开(公告)日：2015-08-20

申请号：US14704300

申请日：2015-05-05

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE ,  FACULTY OF SCIENCE AND TECHNOLOGY NEW UNIVERSITY OF LISBON

Inventor： Sang Hee PARK ,  Chi Sun HWANG ,  Chun Won BYUN ,  Elvira M.C. FORTUNATO ,  Rodrigo F.P. MARTINS ,  Ana R.X. BARROS ,  Nuno F.O. CORREIA ,  Pedro M.C. BARQUINHA ,  Vitor M.L. FIGUEIREDO

IPC: H01L29/786 ,  H01L29/04 ,  H01L29/24

CPC classification number: H01L29/78693 ,  C23C14/08 ,  C23C14/086 ,  C23C14/087 ,  H01L21/02422 ,  H01L21/02565 ,  H01L21/02579 ,  H01L21/02617 ,  H01L21/02628 ,  H01L21/02631 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/04 ,  H01L29/24 ,  H01L29/242 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/94

Abstract: Provided is a semiconductor device using a p-type oxide semiconductor layer and a method of manufacturing the same. The device includes the p-type oxide layer formed of at least one oxide selected from the group consisting of a copper(Cu)-containing copper monoxide, a tin(Sn)-containing tin monoxide, a copper tin oxide containing a Cu—Sn alloy, and a nickel tin oxide containing a Ni—Sn alloy. Thus, transparent or opaque devices are easily developed using the p-type oxide layer. Since an oxide layer that is formed using a low-temperature process is applied to a semiconductor device, the manufacturing process of the semiconductor device is simplified and manufacturing costs may be reduced.

Abstract translation: 提供一种使用p型氧化物半导体层的半导体器件及其制造方法。 该装置包括由至少一种氧化物形成的p型氧化物层，所述氧化物选自由含铜（Cu）的一氧化碳，含锡（Sn）的一氧化锡，含有Cu-Sn的铜锡氧化物 合金和含有Ni-Sn合金的镍锡氧化物。 因此，使用p型氧化物层容易显影透明或不透明的装置。 由于使用低温工艺形成的氧化物层被应用于半导体器件，所以可以简化半导体器件的制造工艺，并且可以降低制造成本。

公开(公告)号：US20230230550A1

公开(公告)日：2023-07-20

申请号：US17940431

申请日：2022-09-08

Applicant: Electronics and Telecommunications Research Institute ,  IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)

Inventor： Chun Won BYUN ,  Chan Mo KANG ,  Nam Sung CHO ,  Byong Deok CHOI ,  Yong Duck KIM

IPC: G09G3/3291

CPC classification number: G09G3/3291 ,  G09G2310/027 ,  G09G2320/0633

Abstract: A pixel circuit driving method of controlling an operation of a light-emitting element provided in a pixel of a display panel may comprise: applying pulse amplitude modulation (PAM) signals having a plurality of levels to a first terminal of a first transistor having a second terminal connected to a control terminal of a second transistor configured to drive the light-emitting element with a current according to a gray scale required for the light-emitting element; and applying a PAM signal of any one level selected from the PAM signals to the control terminal of the second transistor during each sub-frame time corresponding to a turn-on time of the first transistor controlled by a pulse width modulation (PWM) signal having a plurality of sub-frames in a single frame according to the gray scale.

公开(公告)号：US20130189816A1

公开(公告)日：2013-07-25

申请号：US13792436

申请日：2013-03-11

Applicant: Electronics and Telecommunications Research Institute

Inventor： Min Ki RYU ,  Chi Sun HWANG ,  Chun Won BYUN ,  Hye Yong CHU ,  Kyoung Ik CHO

IPC: H01L29/786

CPC classification number: H01L29/66742 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/7869

Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.

公开(公告)号：US20230290306A1

公开(公告)日：2023-09-14

申请号：US18119635

申请日：2023-03-09

Applicant: Electronics and Telecommunications Research Institute ,  IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)

Inventor： Chun Won BYUN ,  Chan Mo KANG ,  Nam Sung CHO ,  Byong Deok CHOI ,  Yong Duck KIM

IPC: G09G3/3233 ,  G09G3/20

CPC classification number: G09G3/3233 ,  G09G3/2096 ,  G09G3/2007 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/08 ,  G09G2330/028 ,  G09G2310/0202 ,  G09G2300/0465 ,  G09G2300/0819

Abstract: A pixel circuit may comprise: a first transistor having a first terminal connected to a data line and to which a data signal is applied and a gate terminal connected to a scan line and to which a scan signal is applied; a third transistor having a gate terminal connected to a second terminal of the first transistor and a second terminal connected to a light emitting device; a capacitor having a second terminal commonly connected to the second terminal of the first transistor and the gate terminal of the third transistor; and a second transistor having a second terminal commonly connected to a first terminal of the capacitor and a first terminal of the third transistor, a first terminal connected to a first power supply voltage, and a gate terminal connected to an emission line to which an emission signal is applied.

公开(公告)号：US20140011297A1

公开(公告)日：2014-01-09

申请号：US14022705

申请日：2013-09-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung Min YOON ,  Chun Won BYUN ,  Shin Hyuk YANG ,  Sang Hee PARK ,  Soon Won JUNG ,  Seung Youl KANG ,  Chi Sun HWANG ,  Byoung Gon YU

IPC: H01L29/66

CPC classification number: H01L29/6684 ,  B82Y10/00 ,  G11C11/22 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/78391

Abstract: Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.

Abstract translation: 提供一种非易失性存储单元及其制造方法。 非易失性存储单元包括存储晶体管和驱动晶体管。 存储晶体管包括设置在基板上的半导体层，缓冲层，有机铁电层和栅极电极。 驱动晶体管包括设置在基板上的半导体层，缓冲层，栅极绝缘层和栅极电极。 存储晶体管和驱动晶体管设置在同一衬底上。 非易失性存储单元在可见光区域是透明的。