公开(公告)号：US5352912A

公开(公告)日：1994-10-04

申请号：US792493

申请日：1991-11-13

申请人： Emmanuel F. Crabbe ,  David L. Harame ,  Bernard S. Meyerson ,  Gary Patton ,  Johannes M. C. Stork

发明人： Emmanuel F. Crabbe ,  David L. Harame ,  Bernard S. Meyerson ,  Gary Patton ,  Johannes M. C. Stork

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/737 ,  H01L29/161 ,  H01L29/72

CPC分类号： H01L29/7378 ,  H01L29/737 ,  Y10S438/936

摘要： A heterojunction bipolar transistor having a single-crystal emitter with reduced charge storage and acceptable current gain is described herein. The heterojunction transistor comprises a collector region, a base region formed on the collector region, and a single-crystal emitter region grown on the base region by low temperature epitaxy. During the formation of the base region, a graded profile of 5-23% germanium is added to the base, as the distance to the collector region decreases, thereby decreasing the base bandgap as it approaches the collector region. Further, during the formation of the emitter region, a graded profile of 0-20% germanium is added to the emitter as the distance from the emitter-base junction increases. Thus, the emitter bandgap decreases as it moves farther from the emitter-base junction. The result of the above grading profiles is that the emitter bandgap is narrower at the emitter contact than the base bandgap at the emitter-base junction.

摘要翻译： 本文描述了具有具有降低的电荷存储和可接受的电流增益的单晶发射极的异质结双极晶体管。 异质结晶体管包括集电极区域，形成在集电极区域上的基极区域和通过低温外延生长在基极区域上的单晶发射极区域。 在形成基极区域时，随着到集电极区域的距离减小，5-23％的锗的梯度分布被添加到基极中，从而随着接近集电极区域而减小基带隙。 此外，在形成发射极区域期间，随着与发射极 - 基极结的距离增加，0-20％锗的梯度轮廓被添加到发射极。 因此，发射极带隙随着与发射极 - 基极结更远地移动而减小。 上述分级曲线的结果是，在发射极接触处的发射极带隙比发射极 - 基极结处的基极带隙更窄。

公开(公告)号：US06908841B2

公开(公告)日：2005-06-21

申请号：US10251453

申请日：2002-09-20

申请人： Lloyd G. Burrell ,  Douglas Kemerer ,  Henry A. Nye, III ,  Hans-Joachim Barth ,  Emmanuel F. Crabbe ,  David Anderson ,  Joseph Chan

发明人： Lloyd G. Burrell ,  Douglas Kemerer ,  Henry A. Nye, III ,  Hans-Joachim Barth ,  Emmanuel F. Crabbe ,  David Anderson ,  Joseph Chan

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L21/44

CPC分类号： H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05546 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

摘要： A semiconductor device (200) having support structures (218, 226, 236) beneath wirebond regions (214) of contact pads (204) and a method of forming same. Low modulus dielectric layers (216, 222, 232) are disposed over a workpiece (212). Support structures (218, 226, 236) are formed in the low modulus dielectric layers (216, 222, 232), and support vias (224, 234) are formed between the support structures (218, 226, 236). A high modulus dielectric film (220, 230) is disposed between each low modulus dielectric layer (216, 222, 232), and a high modulus dielectric layer (256) is disposed over the top low modulus dielectric layer (232). Contact pads (204) are formed in the high modulus dielectric layer (256). Each support via (234) within the low modulus dielectric layer (232) resides directly above a support via (224) in the underlying low modulus dielectric layer (222), to form a plurality of via support stacks within the low modulus dielectric layers (216, 222, 232).

摘要翻译： 一种在接触焊盘（204）的引线键合区域（214）下方具有支撑结构（218,226,236）的半导体器件（200）及其形成方法。 低模量介电层（216,222,232）设置在工件（212）上方。 支撑结构（218,226,236）形成在低模量电介质层（216,222,232）中，并且支撑通孔（224,234）形成在支撑结构（218,226,236）之间。 高模量介电膜（220,230）设置在每个低模量介电层（216,222,232）之间，并且高模量介电层（256）设置在顶部低模量介电层（232）之上。 接触焊盘（204）形成在高模量介电层（256）中。 在低模量介电层（232）内的每个支撑件（234）直接位于下面的低模量介电层（222）中的支撑通孔（224）的上方，以在低模量介电层（222）内形成多个通孔支撑堆叠 216,222,232）。

公开(公告)号：US5485029A

公开(公告)日：1996-01-16

申请号：US268350

申请日：1994-06-30

申请人： Emmanuel F. Crabbe ,  Keith A. Jenkins ,  Jeffrey L. Snare

发明人： Emmanuel F. Crabbe ,  Keith A. Jenkins ,  Jeffrey L. Snare

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/12 ,  H01L29/732 ,  H01L29/72

CPC分类号： H01L27/1203 ,  H01L27/0623 ,  Y10S257/901

摘要： A semiconductor chip having an on-chip ground plane comprising a low resistivity semiconductor region in a plurality of non-device regions of the chip and reach-through regions electrically connected to the low resistivity semiconductor region. One or more front-side contacts are used to electrically connect the reach-through regions and the low resistivity semiconductor region to a ground potential to electrically ground the on-chip ground plane.

摘要翻译： 一种具有片上接地平面的半导体芯片，包括芯片的多个非器件区域中的低电阻率半导体区域和与该低电阻率半导体区域电连接的到达区域。 使用一个或多个前侧触点将通孔区域和低电阻率半导体区域电连接到接地电位，以对片上接地平面电接地。