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公开(公告)号：US06714886B2
公开(公告)日：2004-03-30
申请号：US10207470
申请日：2002-07-29
申请人： Eric C. Sung , Kantilal Bacrania , Hsin-Shu Chen , J. Mikko Hakkarainen , Bang-Sup Song , Brian L. Allen , Mario Sanchez
发明人： Eric C. Sung , Kantilal Bacrania , Hsin-Shu Chen , J. Mikko Hakkarainen , Bang-Sup Song , Brian L. Allen , Mario Sanchez
IPC分类号： H03M112
摘要： A compensation system for calibrating an amplifier having a compensation input including a sigma delta converter, a counter, a memory, adjust logic, a DAC, a pair of compensation capacitors, and a pair of current to voltage (I/V) converters. The converter converts an offset voltage to a bit stream. The counter stores a sum value indicative of the output offset. The memory stores a digital bias value. The adjust logic determines an adjust value based on the sum value and adjusts the stored digital bias value based on the adjust value. The DAC converts the digital bias value to a differential bias current. The compensation capacitors apply a compensation voltage to a compensation input of the amplifier. The I/V converters charge the compensation capacitors using the differential bias current. The adjust logic may use upper and lower thresholds and adjust the digital bias value by one LSB for each compensation cycle.
摘要翻译： 一种用于校准具有包括Σ-Δ转换器，计数器，存储器，调整逻辑，DAC，一对补偿电容器和一对电流 - 电压（I / V）转换器的补偿输入的放大器的补偿系统。 转换器将偏移电压转换为位流。 计数器存储表示输出偏移量的和值。 存储器存储数字偏置值。 调整逻辑基于和值确定调整值，并根据调整值调整存储的数字偏置值。 DAC将数字偏置值转换为差分偏置电流。 补偿电容器将补偿电压施加到放大器的补偿输入。 I / V转换器使用差分偏置电流对补偿电容器充电。 调整逻辑可以使用上限和下限阈值，并且在每个补偿周期内将数字偏置值调整一个LSB。
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2.发明授权公开(公告)号：US06628216B2
公开(公告)日：2003-09-30
申请号：US10207340
申请日：2002-07-29
申请人： Hsin-Shu Chen , Kantilal Bacrania , Eric C. Sung , J. Mikko Hakkarainen , Bang-Sup Song , Brian L. Allen , Mario Sanchez
发明人： Hsin-Shu Chen , Kantilal Bacrania , Eric C. Sung , J. Mikko Hakkarainen , Bang-Sup Song , Brian L. Allen , Mario Sanchez
IPC分类号： H03M110
摘要： A calibration system and method for a resistor ladder that employs relative measurement and adjustment between pairs of resistors. The system includes a resistor tree of complementary pairs of programmable resistors coupled to the resistor ladder, a measurement circuit that measures voltage differences between complementary pairs of programmable resistors, and control logic. The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and adjusts the relative resistance of each complementary pair of programmable resistors to equalize voltage. The measurement is facilitated by a sigma-delta ADC that converts a measured voltage difference into a bit stream. The programmable resistors are implemented with binary weighted resistors that are digitally adjusted one LSB at a time. Lower and upper adjustment thresholds may be employed to avoid unnecessary over-adjustments while maintaining a requisite level of accuracy.
摘要翻译： 一种用于电阻梯的校准系统和方法，其采用电阻对之间的相对测量和调整。 该系统包括耦合到电阻梯的互补对可编程电阻器的电阻树，测量电路，其测量互补对可编程电阻器和控制逻辑之间的电压差。 控制逻辑控制测量电路来测量每对互补的可编程电阻之间的电压差，并调整每对互补可编程电阻对的相对电阻以均衡电压。 通过将测量的电压差转换为比特流的Σ-ΔADC便于测量。 可编程电阻通过二进制加权电阻实现，每次一个LSB数字调节。 可以采用较低和较高的调整阈值，以避免不必要的过度调整，同时保持必要的精度水平。
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公开(公告)号：US06570523B1
公开(公告)日：2003-05-27
申请号：US10097677
申请日：2002-03-13
申请人： Kantilal Bacrania , Hsin-Shu Chen , Eric C. Sung , Bang-Sup Song , J. Mikko Hakkarainen , Brian L. Allen , Mario Sanchez
发明人： Kantilal Bacrania , Hsin-Shu Chen , Eric C. Sung , Bang-Sup Song , J. Mikko Hakkarainen , Brian L. Allen , Mario Sanchez
IPC分类号： H03M112
摘要： A multistage ADC that subranges and interpolates, and that amplifies selected subranges to convert an analog signal to a stream of digital values. The ADC samples the analog signal and provides a stream of sample signals. A first stage flash converts each sample signal into a first multiple bit value and subranges a reference ladder according to the first multiple bit value into selected reference signals. Each additional secondary stage amplifies a selected subrange of signals from a prior stage, flash converts the amplified residual signals to provide an additional multiple bit value, interpolates each set of amplified residual signals and subranges the interpolated signals according to the corresponding multiple bit value. A final stage amplifies and flash converts to determine a final multiple bit value. An error corrector combines each set of multiple bit values into a digital value.
摘要翻译： 一种多级ADC，用于对所选择的子范围进行放大和内插，以将模拟信号转换为数字值流。 ADC对模拟信号进行采样，并提供一个采样信号流。 第一级闪存将每个采样信号转换为第一多位值，并将根据第一多位值的参考梯形图子化为选定的参考信号。 每个附加的次级放大来自前一级的所选择的子信号，闪存转换放大的残留信号以提供附加的多位值，内插每组放大的残留信号，并根据相应的多位值对内插信号进行子范围调整。 最后一级放大并进行闪存转换，以确定最终的多位值。 误差校正器将每组多个位值组合成一个数字值。
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公开(公告)号：US06731155B2
公开(公告)日：2004-05-04
申请号：US10308775
申请日：2002-12-03
申请人： J. Mikko Hakkarainen , Kantilal Bacrania , Eric C. Sung , Hsin-Shu Chen , Bang-Sup Song , Mario Sanchez
发明人： J. Mikko Hakkarainen , Kantilal Bacrania , Eric C. Sung , Hsin-Shu Chen , Bang-Sup Song , Mario Sanchez
IPC分类号： H03K1716
摘要： A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGS—VT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.
摘要翻译： 双泵电路，包括传输门和双电荷泵。 传输门包括一个p沟道晶体管和一个n沟道晶体管，每个具有一个控制端子和一对电流端子，耦合在一个双泵输入端和一个双泵输出端之间。 双电荷泵包括第一和第二泵电路，其中每个泵电路耦合到双泵输入和相应的一个传输栅晶体管的控制端。 每个泵电路通过维持VGS-VT恒定而使其对应的传输门晶体管的操作线性化。 双泵电路用于包括至少一个双泵采样电路，至少一个采样电容器和用于控制输入信号采样定时的控制电路的跟踪和保持电路。 每个双泵采样电路包括传输门和双电荷泵。
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5.发明授权
公开(公告)号：US6118398A
公开(公告)日：2000-09-12
申请号：US149154
申请日：1998-09-08
CPC分类号： H03M1/0653 , H03M1/687 , H03M1/745 , H03M1/747
摘要： A digital-to-analog converter (DAC) includes a plurality of current sources on a substrate operable in a predetermined sequence of use for generating an output current based upon a digital input, and a connection network for establishing the predetermined sequence of use for the current sources based upon the actual current values and to increase performance of the DAC. For example, the predetermined sequence of use can be set to reduce integral non-linearity error of the DAC. The connection network may be provided by a plurality of fusible links selectively connected to set the predetermined sequence of use. The current sources may include a first group of most significant bit (MSB) current sources for a predetermined number of MSBs. In addition, the plurality of current sources may include a second group of mid-most significant bit (mid MSBs) current sources for a predetermined number of mid MSBs. The plurality of current sources have actual values sortable from lowest to highest, and each actual current value will define an error value with both a magnitude and polarity relative to the desired value. One embodiment for sorting the order of use of the current sources is based upon the error values.
摘要翻译： 数模转换器（DAC）包括在基板上的多个电流源，其可以按照预定的使用顺序操作，用于基于数字输入产生输出电流;以及连接网络，用于建立用于 基于实际电流值的电流源和增加DAC的性能。 例如，可以设定预定的使用顺序以减小DAC的积分非线性误差。 连接网络可以由选择性地连接以设置预定使用顺序的多个可熔链路提供。 当前源可以包括用于预定数量的MSB的第一组最高有效位（MSB）电流源。 另外，多个电流源可以包括用于预定数量的中间MSB的第二组最高有效位（中间MSB）电流源。 多个电流源具有从最低到最高的实际值，并且每个实际电流值将定义具有相对于期望值的幅度和极性的误差值。 用于对当前源的使用顺序进行排序的一个实施例基于错误值。
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6.发明授权Analog-to-digital converter having enhanced accuracy gain stage, and associated devices and methods 有权具有增强的精度增益级的模数转换器以及相关的器件和方法
公开(公告)号：US6107950A
公开(公告)日：2000-08-22
申请号：US148955
申请日：1998-09-08
CPC分类号： H03M1/1057 , H03M1/167
摘要： An analog-to-digital converter (ADC) includes a plurality of capacitors formed on a semiconductor substrate and having actual capacitance values statistically related to desired capacitance values, and a gain stage comprising an amplifier and capacitors selected to provide a more accurate gain for the gain stage. A first at least one capacitor is connected between an input and an output of the amplifier defining a feedback capacitance, and a second at least one capacitor is connected between the input of the amplifier and an input of the at least one gain stage defining an input capacitance. In addition, the ADC includes a connection network selectively connecting the first at least one capacitor and the second at least one capacitor from among the plurality of capacitors to provide a desired ratio of feedback capacitance to input capacitance based upon the actual capacitance values. Accordingly, a gain can be set for the gain stage that is more accurate than would otherwise be obtained. The high accuracy switched capacitor gain stage may be used in other applications.
摘要翻译： 模数转换器（ADC）包括形成在半导体衬底上的多个电容器，其具有与期望电容值统计相关的实际电容值，增益级包括放大器和选择的电容器，以为 增益阶段 第一至少一个电容器连接在定义反馈电容的放大器的输入和输出之间，并且第二至少一个电容器连接在放大器的输入端和至少一个增益级的输入端之间， 电容。 此外，ADC包括连接网络，其选择性地连接多个电容器中的第一至少一个电容器和第二至少一个电容器，以根据实际电容值提供所需的反馈电容与输入电容的比值。 因此，可以为增益级设置增益，该增益比其它方式更准确。 高精度开关电容器增益级可用于其他应用。
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公开(公告)号：US06635237B2
公开(公告)日：2003-10-21
申请号：US10049061
申请日：2002-06-10
IPC分类号： A61K964
CPC分类号： A61K31/46
摘要： The present invention relates to a pharmaceutical composition comprising cocaethylene as active ingredient and to its use in treating dependence on psychoactive substances, in particular on cocaine.
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公开(公告)号：USD695205S1
公开(公告)日：2013-12-10
申请号：US29429804
申请日：2012-08-16
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9.发明授权公开(公告)号：US07615945B2
公开(公告)日：2009-11-10
申请号：US11607249
申请日：2006-12-01
CPC分类号： E05F15/611 , E05Y2900/40
摘要： In one embodiment, the present invention describes a gate closure system having a barrier or gate operator for moving a gate between a gate fully opened position and a gate fully closed position. The gate closure system preferably further includes, among other things, a master control board with input and output points to receive and transmit data associated with movement of the gate, including a panic control override mode circuit input to the master control board that negates all gate movement parameters during any portion of the gate's travel path to open or close the gate at a substantially greater rate of speed than typically used to open or close the gate during normal operation, regardless of the gate's speed, torque, direction of travel (forward or backward), or whether the gate is stationary.
摘要翻译： 在一个实施例中，本发明描述了一种门关闭系统，其具有用于在门完全打开位置和门完全关闭位置之间移动门的屏障或门操作器。 门关闭系统优选还包括主控制板，其具有用于接收和发送与门的移动有关的数据的输入和输出点的主控制板，包括输入到主控制板的紧急控制超控模式电路，其将所有门 在门的行进路径的任何部分中的移动参数，以在正常操作期间以比通常用于打开或关闭门的速度大得多的速度来打开或关闭门，而与门的速度，转矩，行进方向无关（向前或向前 向后），或者门是静止的。
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公开(公告)号：USD997154S1
公开(公告)日：2023-08-29
申请号：US29770484
申请日：2021-02-12
申请人： Mario Sanchez
设计人： Mario Sanchez , Wayne Holt
摘要： FIG. 1 is a perspective view of an electronic device stand showing our new design;
FIG. 2 is a front elevational view thereof;
FIG. 3 is a rear elevational view thereof;
FIG. 4 is a right side view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a top plan view thereof;
FIG. 7 is a bottom plan thereof; and,
FIG. 8 is an exploded view thereof.
The broken lines in the drawings illustrate portions of the electronic device stand that form no part of the claimed design.
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