公开(公告)号：US06714886B2

公开(公告)日：2004-03-30

申请号：US10207470

申请日：2002-07-29

申请人： Eric C. Sung ,  Kantilal Bacrania ,  Hsin-Shu Chen ,  J. Mikko Hakkarainen ,  Bang-Sup Song ,  Brian L. Allen ,  Mario Sanchez

发明人： Eric C. Sung ,  Kantilal Bacrania ,  Hsin-Shu Chen ,  J. Mikko Hakkarainen ,  Bang-Sup Song ,  Brian L. Allen ,  Mario Sanchez

IPC分类号： H03M112

CPC分类号： H03M1/165 ,  H03M1/365

摘要： A compensation system for calibrating an amplifier having a compensation input including a sigma delta converter, a counter, a memory, adjust logic, a DAC, a pair of compensation capacitors, and a pair of current to voltage (I/V) converters. The converter converts an offset voltage to a bit stream. The counter stores a sum value indicative of the output offset. The memory stores a digital bias value. The adjust logic determines an adjust value based on the sum value and adjusts the stored digital bias value based on the adjust value. The DAC converts the digital bias value to a differential bias current. The compensation capacitors apply a compensation voltage to a compensation input of the amplifier. The I/V converters charge the compensation capacitors using the differential bias current. The adjust logic may use upper and lower thresholds and adjust the digital bias value by one LSB for each compensation cycle.

摘要翻译： 一种用于校准具有包括Σ-Δ转换器，计数器，存储器，调整逻辑，DAC，一对补偿电容器和一对电流 - 电压（I / V）转换器的补偿输入的放大器的补偿系统。 转换器将偏移电压转换为位流。 计数器存储表示输出偏移量的和值。 存储器存储数字偏置值。 调整逻辑基于和值确定调整值，并根据调整值调整存储的数字偏置值。 DAC将数字偏置值转换为差分偏置电流。 补偿电容器将补偿电压施加到放大器的补偿输入。 I / V转换器使用差分偏置电流对补偿电容器充电。 调整逻辑可以使用上限和下限阈值，并且在每个补偿周期内将数字偏置值调整一个LSB​​。

公开(公告)号：US06628216B2

公开(公告)日：2003-09-30

申请号：US10207340

申请日：2002-07-29

申请人： Hsin-Shu Chen ,  Kantilal Bacrania ,  Eric C. Sung ,  J. Mikko Hakkarainen ,  Bang-Sup Song ,  Brian L. Allen ,  Mario Sanchez

发明人： Hsin-Shu Chen ,  Kantilal Bacrania ,  Eric C. Sung ,  J. Mikko Hakkarainen ,  Bang-Sup Song ,  Brian L. Allen ,  Mario Sanchez

IPC分类号： H03M110

CPC分类号： H03M1/165 ,  H03M1/365

摘要： A calibration system and method for a resistor ladder that employs relative measurement and adjustment between pairs of resistors. The system includes a resistor tree of complementary pairs of programmable resistors coupled to the resistor ladder, a measurement circuit that measures voltage differences between complementary pairs of programmable resistors, and control logic. The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and adjusts the relative resistance of each complementary pair of programmable resistors to equalize voltage. The measurement is facilitated by a sigma-delta ADC that converts a measured voltage difference into a bit stream. The programmable resistors are implemented with binary weighted resistors that are digitally adjusted one LSB at a time. Lower and upper adjustment thresholds may be employed to avoid unnecessary over-adjustments while maintaining a requisite level of accuracy.

摘要翻译： 一种用于电阻梯的校准系统和方法，其采用电阻对之间的相对测量和调整。 该系统包括耦合到电阻梯的互补对可编程电阻器的电阻树，测量电路，其测量互补对可编程电阻器和控制逻辑之间的电压差。 控制逻辑控制测量电路来测量每对互补的可编程电阻之间的电压差，并调整每对互补可编程电阻对的相对电阻以均衡电压。 通过将测量的电压差转换为比特流的Σ-ΔADC便于测量。 可编程电阻通过二进制加权电阻实现，每次一个LSB​​数字调节。 可以采用较低和较高的调整阈值，以避免不必要的过度调整，同时保持必要的精度水平。

公开(公告)号：US06570523B1

公开(公告)日：2003-05-27

申请号：US10097677

申请日：2002-03-13

申请人： Kantilal Bacrania ,  Hsin-Shu Chen ,  Eric C. Sung ,  Bang-Sup Song ,  J. Mikko Hakkarainen ,  Brian L. Allen ,  Mario Sanchez

发明人： Kantilal Bacrania ,  Hsin-Shu Chen ,  Eric C. Sung ,  Bang-Sup Song ,  J. Mikko Hakkarainen ,  Brian L. Allen ,  Mario Sanchez

IPC分类号： H03M112

CPC分类号： H03M1/165 ,  H03M1/365

摘要： A multistage ADC that subranges and interpolates, and that amplifies selected subranges to convert an analog signal to a stream of digital values. The ADC samples the analog signal and provides a stream of sample signals. A first stage flash converts each sample signal into a first multiple bit value and subranges a reference ladder according to the first multiple bit value into selected reference signals. Each additional secondary stage amplifies a selected subrange of signals from a prior stage, flash converts the amplified residual signals to provide an additional multiple bit value, interpolates each set of amplified residual signals and subranges the interpolated signals according to the corresponding multiple bit value. A final stage amplifies and flash converts to determine a final multiple bit value. An error corrector combines each set of multiple bit values into a digital value.

摘要翻译： 一种多级ADC，用于对所选择的子范围进行放大和内插，以将模拟信号转换为数字值流。 ADC对模拟信号进行采样，并提供一个采样信号流。 第一级闪存将每个采样信号转换为第一多位值，并将根据第一多位值的参考梯形图子化为选定的参考信号。 每个附加的次级放大来自前一级的所选择的子信号，闪存转换放大的残留信号以提供附加的多位值，内插每组放大的残留信号，并根据相应的多位值对内插信号进行子范围调整。 最后一级放大并进行闪存转换，以确定最终的多位值。 误差校正器将每组多个位值组合成一个数字值。

公开(公告)号：US06731155B2

公开(公告)日：2004-05-04

申请号：US10308775

申请日：2002-12-03

申请人： J. Mikko Hakkarainen ,  Kantilal Bacrania ,  Eric C. Sung ,  Hsin-Shu Chen ,  Bang-Sup Song ,  Mario Sanchez

发明人： J. Mikko Hakkarainen ,  Kantilal Bacrania ,  Eric C. Sung ,  Hsin-Shu Chen ,  Bang-Sup Song ,  Mario Sanchez

IPC分类号： H03K1716

CPC分类号： H03M1/165 ,  H03M1/365

摘要： A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGS—VT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.

摘要翻译： 双泵电路，包括传输门和双电荷泵。 传输门包括一个p沟道晶体管和一个n沟道晶体管，每个具有一个控制端子和一对电流端子，耦合在一个双泵输入端和一个双泵输出端之间。 双电荷泵包括第一和第二泵电路，其中每个泵电路耦合到双泵输入和相应的一个传输栅晶体管的控制端。 每个泵电路通过维持VGS-VT恒定而使其对应的传输门晶体管的操作线性化。 双泵电路用于包括至少一个双泵采样电路，至少一个采样电容器和用于控制输入信号采样定时的控制电路的跟踪和保持电路。 每个双泵采样电路包括传输门和双电荷泵。

公开(公告)号：US6118398A

公开(公告)日：2000-09-12

申请号：US149154

申请日：1998-09-08

申请人： Gregory J. Fisher ,  Mario Sanchez ,  Kantilal Bacrania

发明人： Gregory J. Fisher ,  Mario Sanchez ,  Kantilal Bacrania

IPC分类号： H03M1/06 ,  H03M1/68 ,  H03M1/74 ,  H03M1/66

CPC分类号： H03M1/0653 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

摘要： A digital-to-analog converter (DAC) includes a plurality of current sources on a substrate operable in a predetermined sequence of use for generating an output current based upon a digital input, and a connection network for establishing the predetermined sequence of use for the current sources based upon the actual current values and to increase performance of the DAC. For example, the predetermined sequence of use can be set to reduce integral non-linearity error of the DAC. The connection network may be provided by a plurality of fusible links selectively connected to set the predetermined sequence of use. The current sources may include a first group of most significant bit (MSB) current sources for a predetermined number of MSBs. In addition, the plurality of current sources may include a second group of mid-most significant bit (mid MSBs) current sources for a predetermined number of mid MSBs. The plurality of current sources have actual values sortable from lowest to highest, and each actual current value will define an error value with both a magnitude and polarity relative to the desired value. One embodiment for sorting the order of use of the current sources is based upon the error values.

摘要翻译： 数模转换器（DAC）包括在基板上的多个电流源，其可以按照预定的使用顺序操作，用于基于数字输入产生输出电流;以及连接网络，用于建立用于 基于实际电流值的电流源和增加DAC的性能。 例如，可以设定预定的使用顺序以减小DAC的积分非线性误差。 连接网络可以由选择性地连接以设置预定使用顺序的多个可熔链路提供。 当前源可以包括用于预定数量的MSB的第一组最高有效位（MSB）电流源。 另外，多个电流源可以包括用于预定数量的中间MSB的第二组最高有效位（中间MSB）电流源。 多个电流源具有从最低到最高的实际值，并且每个实际电流值将定义具有相对于期望值的幅度和极性的误差值。 用于对当前源的使用顺序进行排序的一个实施例基于错误值。

公开(公告)号：US6107950A

公开(公告)日：2000-08-22

申请号：US148955

申请日：1998-09-08

申请人： Gregory J. Fisher ,  Mario Sanchez ,  Kantilal Bacrania

发明人： Gregory J. Fisher ,  Mario Sanchez ,  Kantilal Bacrania

IPC分类号： H03M1/10 ,  H03M1/16 ,  H03M1/12

CPC分类号： H03M1/1057 ,  H03M1/167

摘要： An analog-to-digital converter (ADC) includes a plurality of capacitors formed on a semiconductor substrate and having actual capacitance values statistically related to desired capacitance values, and a gain stage comprising an amplifier and capacitors selected to provide a more accurate gain for the gain stage. A first at least one capacitor is connected between an input and an output of the amplifier defining a feedback capacitance, and a second at least one capacitor is connected between the input of the amplifier and an input of the at least one gain stage defining an input capacitance. In addition, the ADC includes a connection network selectively connecting the first at least one capacitor and the second at least one capacitor from among the plurality of capacitors to provide a desired ratio of feedback capacitance to input capacitance based upon the actual capacitance values. Accordingly, a gain can be set for the gain stage that is more accurate than would otherwise be obtained. The high accuracy switched capacitor gain stage may be used in other applications.

摘要翻译： 模数转换器（ADC）包括形成在半导体衬底上的多个电容器，其具有与期望电容值统计相关的实际电容值，增益级包括放大器和选择的电容器，以为 增益阶段 第一至少一个电容器连接在定义反馈电容的放大器的输入和输出之间，并且第二至少一个电容器连接在放大器的输入端和至少一个增益级的输入端之间， 电容。 此外，ADC包括连接网络，其选择性地连接多个电容器中的第一至少一个电容器和第二至少一个电容器，以根据实际电容值提供所需的反馈电容与输入电容的比值。 因此，可以为增益级设置增益，该增益比其它方式更准确。 高精度开关电容器增益级可用于其他应用。

公开(公告)号：US06329260B1

公开(公告)日：2001-12-11

申请号：US09394802

申请日：1999-09-10

申请人： Glenn Alan DeJong ,  Akira Ito ,  Choong-Sun Rhee ,  Jeffrey Johnston ,  Michael D. Church ,  Kantilal Bacrania

发明人： Glenn Alan DeJong ,  Akira Ito ,  Choong-Sun Rhee ,  Jeffrey Johnston ,  Michael D. Church ,  Kantilal Bacrania

IPC分类号： H01L21331

CPC分类号： G05F3/30 ,  G05F3/262 ,  G11C5/143 ,  G11C27/026 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0688 ,  H03F1/523 ,  H03F3/505 ,  H03F2200/294 ,  H03G1/0082 ,  H03K5/15 ,  H03K17/223 ,  H03K2217/0018 ,  H03M1/162 ,  H03M1/365

摘要： An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat, digital CMOS devices are formed behind the other moat.

摘要翻译： 集成电路具有双二极管护城河形式的隔离结构。 P衬底在N +掩埋层8605的相对侧上具有P +掩埋层8601和8602.在一个二极管护套之后形成模拟器件，在另一个护城河之后形成数字CMOS器件。

公开(公告)号：US5059982A

公开(公告)日：1991-10-22

申请号：US587089

申请日：1990-09-24

申请人： Kantilal Bacrania ,  Chong I. Chi

发明人： Kantilal Bacrania ,  Chong I. Chi

IPC分类号： H03M1/08 ,  H03M1/46 ,  H03M1/80

CPC分类号： H03M1/0836 ,  H03M1/466 ,  H03M1/804

摘要： Analog to digital conversion begins by terminating the acquisition phase of the analog input signal and immediately starting the successive approximation conversion phase upon receipt of a start conversion command. Upon the completion of the successive approximation conversion phase and latching the result, the array is rest if required. The comparator offset is sampled-and-held, if required, and the acquisition phase is initiated and continues until the receipt or occurrence of the next start conversion command.

摘要翻译： 模拟数字转换通过终止模拟输入信号的采集阶段开始，并在接收到开始转换命令后立即开始逐次逼近转换阶段。 在逐次逼近转换阶段完成并锁存结果后，如果需要，阵列就会休息。 如果需要，比较器偏移被采样保持，并且采集阶段被启动并继续，直到接收或发生下一个启动转换命令。

公开(公告)号：US4897567A

公开(公告)日：1990-01-30

申请号：US257015

申请日：1988-10-13

申请人： Kantilal Bacrania

发明人： Kantilal Bacrania

IPC分类号： H03K3/356

CPC分类号： H03K3/356104

摘要： A level translator having a pair of cross-coupled pull-down field effect transistors, a pair of pull-up transistors, and a pair of additinal pull-down transistors wherein the additional pull-down transistors are operable to be on to initially pull down the respective node and the first pair of pull down transistors turn on to finish the pull down. The additional pull-down transistors became ineffective while the first pair of pull-down transistors are turned on hard.

摘要翻译： 具有一对交叉耦合下拉场效应晶体管，一对上拉晶体管和一对附加下拉晶体管的电平转换器，其中附加下拉晶体管可操作以开始下拉 相应的节点和第一对下拉晶体管导通以完成下拉。 附加的下拉晶体管变得无效，而第一对下拉晶体管变硬。

公开(公告)号：US5481129A

公开(公告)日：1996-01-02

申请号：US391490

申请日：1995-02-21

申请人： Glenn A. DeJong ,  Kantilal Bacrania ,  Michael D. Church ,  Gregory J. Fisher ,  John T. Gasner ,  Akira Ito ,  Jeffrey M. Johnston ,  Dave Kutchmarick ,  Choong-Sun Rhee

发明人： Glenn A. DeJong ,  Kantilal Bacrania ,  Michael D. Church ,  Gregory J. Fisher ,  John T. Gasner ,  Akira Ito ,  Jeffrey M. Johnston ,  Dave Kutchmarick ,  Choong-Sun Rhee

IPC分类号： G05F3/30 ,  G11C27/02 ,  H01L21/8249 ,  H01L27/02 ,  H01L27/06 ,  H03F1/52 ,  H03F3/50 ,  H03G1/00 ,  H03K5/15 ,  H03K17/22 ,  H03M1/16 ,  H03M1/36 ,  H01L29/8605

CPC分类号： H03K5/15 ,  G05F3/30 ,  G11C27/026 ,  H01L21/8249 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0688 ,  H03F1/523 ,  H03F3/505 ,  H03G1/0082 ,  H03K17/223 ,  H03M1/162 ,  H03F2200/294 ,  H03M1/365

摘要： A two-step analog-to-digital converter and BiCMOS fabrication method. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from the analog devices. The converter uses NPN current switching in a flash analog-to-digital converter and in a digital-to-analog converter for low noise operation. CMOS digital error correction and BiCMOS output drivers provide high packing density plus large output load handling. Timing control aggregates switching events and puts them into intervals when noise sensitive operations are inactive. The fabrication method uses a thin epitaxial layer with limited thermal processing to provide NPN and PNP devices with large breakdown and Early voltages. Laser trimmed resistors provide small long term drift due to dopant stabilization in underlying BPSG and low hydrogen nitride passivation.

摘要翻译： 两步模拟 - 数字转换器和BiCMOS制造方法。 该制造方法提供了数字CMOS器件与模拟器件的伪衬底隔离。 转换器在闪存模数转换器和数模转换器中使用NPN电流切换，以实现低噪声运行。 CMOS数字纠错和BiCMOS输出驱动器提供高封装密度和大输出负载处理。 定时控制聚合切换事件，并在噪声敏感操作无效时将其置于间隔。 该制造方法使用具有有限热处理的薄外延层来为NPN和PNP器件提供大的击穿和早期电压。 激光修整电阻器由于在底层BPSG和低氮化氢钝化中的掺杂剂稳定性而提供较小的长期漂移。