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公开(公告)号：US20110289337A1
公开(公告)日：2011-11-24
申请号：US13147429
申请日：2009-02-27
IPC分类号： G06F1/28
CPC分类号： G06F1/26
摘要： Reporting electrical current to a processor. At least some of the illustrative embodiments are methods including providing operational power to a processor at a voltage indicated by the processor of a computer system, measuring electrical current actually drawn by the processor, and reporting to the processor a value of electrical current drawn by the processor. The value of electrical current reported different than the electrical current actually drawn by more than a measurement error of measuring the electrical current actually drawn.
摘要翻译： 向处理器报告电流。 示例性实施例中的至少一些是包括以计算机系统的处理器指示的电压向处理器提供操作功率的方法，测量由处理器实际绘制的电流，并向处理器报告由该处理器绘制的电流值 处理器。 报告的电流值实际上与实际绘制的电流的测量误差大于实际绘制的电流值。
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公开(公告)号：US08843776B2
公开(公告)日：2014-09-23
申请号：US13147429
申请日：2009-02-27
CPC分类号： G06F1/26
摘要： Reporting electrical current to a processor. At least some of the illustrative embodiments are methods including providing operational power to a processor at a voltage indicated by the processor of a computer system, measuring electrical current actually drawn by the processor, and reporting to the processor a value of electrical current drawn by the processor. The value of electrical current reported different than the electrical current actually drawn by more than a measurement error of measuring the electrical current actually drawn.
摘要翻译： 向处理器报告电流。 示例性实施例中的至少一些是包括以计算机系统的处理器指示的电压向处理器提供操作功率的方法，测量由处理器实际绘制的电流，并向处理器报告由该处理器绘制的电流值 处理器。 报告的电流值实际上与实际绘制的电流的测量误差大于实际绘制的电流值。
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公开(公告)号：US20120260015A1
公开(公告)日：2012-10-11
申请号：US13082282
申请日：2011-04-07
IPC分类号： G06F13/14
CPC分类号： G06F13/409 , G06F2213/0026
摘要： Peripheral Component Interconnect Express (“PCIe”) Port bifurcation systems and methods are provided. An illustrative PCIe port bifurcation card can include: a PCIe interface and a plurality of PCIe devices, each independently coupled to the interface via an unswitched connection. The card can further include a read only memory (ROM) coupled to the interface, the ROM can include bifurcation data. A clocking signal replicator can be coupled to the interface to: replicate a reference clock signal received via the interface and provide the replicated reference dock signal to each of the plurality of PCIe devices.
摘要翻译： 提供外围组件互连Express（PCIe）端口分岔系统和方法。 说明性的PCIe端口分叉卡可以包括：PCIe接口和多个PCIe设备，每个PCIe设备经由非切换的连接独立地耦合到接口。 卡还可以包括耦合到接口的只读存储器（ROM），ROM可以包括分岔数据。 时钟信号复制器可以耦合到接口以：复制经由接口接收的参考时钟信号，并将复制的参考基站信号提供给多个PCIe设备中的每一个。
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公开(公告)号：US06772295B2
公开(公告)日：2004-08-03
申请号：US10322222
申请日：2002-12-17
IPC分类号： G06F1200
CPC分类号： G06F12/0875 , G06F12/0862 , G06F2212/6028
摘要： The present invention is generally directed to a system and method for fetching data from system memory to a device in communication with the system over a PCI bus, via an I/O cache. Broadly, the present invention may be viewed as a novel way to communicate certain fetching hints; namely, hints that specify certain qualities about the data that is to be fetched from the system memory. In operation, the I/O cache may use such hints to more effectively manage the data that passes through it. As simply one example, if, based upon the hints, the controller for the I/O cache knew (or assumed) that the data being fetched was ATM data, then it would also know (based upon the nature of ATM data) that precisely a forty-eight byte data payload was to be sent to the requesting device, and the I/O cache could pre-fetch precisely this amount of data (typically one or two cache lines). In accordance with one-aspect of the invention, such a system includes an input/output (I/O) cache memory interposed between the system memory and the PCI bus, wherein the cache memory has internal memory space in the form of a plurality of data lines within the cache memory. The system further includes a plurality of registers for each PCI master that are configured to define fetching criteria. Finally, the system includes a register selector that is configured to select an active register among the plurality of registers, wherein fetching criteria for the device is specified by the active register.
摘要翻译： 本发明一般涉及一种系统和方法，用于经由I / O高速缓存将数据从系统存储器提取到与PCI总线通信的设备。 概括地说，本发明可以被看作是传达某些提取提示的新颖方式; 即指定要从系统内存中提取的数据的某些质量的提示。 在操作中，I / O缓存可以使用这样的提示来更有效地管理通过它的数据。 作为一个例子，如果基于提示，I / O缓存的控制器知道（或假设）所取出的数据是ATM数据，则它也将精确地知道（基于ATM数据的性质）， 将48个字节的数据有效载荷发送到请求设备，并且I / O缓存可以精确地预取这一数量的数据（通常为一个或两个高速缓存行）。 根据本发明的一个方面，这种系统包括插入在系统存储器和PCI总线之间的输入/输出（I / O）高速缓冲存储器，其中高速缓冲存储器具有多个形式的内部存储器空间 高速缓存中的数据线。 该系统还包括用于每个PCI主机的多个寄存器，其被配置为定义提取准则。 最后，该系统包括一个寄存器选择器，被配置为在多个寄存器中选择一个活动寄存器，其中由该寄存器指定该设备的取得标准。
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公开(公告)号：US20130173901A1
公开(公告)日：2013-07-04
申请号：US13821506
申请日：2010-11-01
申请人： Raphael Gay , Robert J. Horning
发明人： Raphael Gay , Robert J. Horning
IPC分类号： G06F9/44
CPC分类号： G06F9/4405 , G06F13/12 , G06F13/4068
摘要： Multi-processor computer systems and methods are provided. A multi-processor computer system can include a plurality of communicatively coupled processors (1101-N), each coupled to a common motherboard (120) and each associated with a memory (1401-N). The system can include a boot code (130) executable from at least one of a standard mode and an independent mode. The plurality of communicatively coupled processors can execute one instance of the boot code in standard mode and at least a portion of the plurality of communicatively coupled processors can execute one instance of the boot code in independent mode.
摘要翻译： 提供多处理器计算机系统和方法。 多处理器计算机系统可以包括多个通信耦合处理器（1101-N），每个处理器耦合到公共母板（120），并且每个处理器与存储器（1401-N）相关联。 该系统可以包括可从标准模式和独立模式中的至少一个执行的引导代码（130）。 多个通信耦合的处理器可以以标准模式执行引导代码的一个实例，并且多个通信耦合的处理器的至少一部分可以以独立模式执行引导代码的一个实例。
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6.发明授权Low skew system for interfacing asics by routing internal clock off-chip to external delay element then feeding back to on-chip drivers 失效低偏移系统，用于通过将外部时钟片外到外部延迟元件，然后反馈到片上驱动器进行接口连接
公开(公告)号：US5416918A
公开(公告)日：1995-05-16
申请号：US187264
申请日：1994-01-27
CPC分类号： G06F1/10
摘要： A low skew interface system for enabling an ASIC chip's receivers to latch information from one or more buses. The interface comprises a driver circuit connected to an internal clock of the chip for generating another clock signal with phase different from the phase of the internal clock. A delay element is located off the chip and connected to the driver circuit for delaying the clock signal, thereby generating a latch clock signal. The latch clock signal is sent back on-chip to enable the receivers to transfer information from one of the buses to the chip.
摘要翻译： 低偏移接口系统，用于使ASIC芯片的接收器能够锁存来自一个或多个总线的信息。 该接口包括连接到芯片的内部时钟的驱动器电路，用于产生具有不同于内部时钟的相位的相位的另一个时钟信号。 延迟元件位于芯片外并连接到驱动器电路，用于延迟时钟信号，从而产生锁存时钟信号。 锁存时钟信号在芯片上被送回，以使接收器能够将信息从一个总线传送到芯片。
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公开(公告)号：US06465121B1
公开(公告)日：2002-10-15
申请号：US09652249
申请日：2000-08-30
IPC分类号： H01M238
CPC分类号： H01M2/38 , H01M2/0275 , H01M2/36 , H01M6/38 , H01M10/04 , H01M10/0436 , H01M10/0525 , H01M10/4214
摘要： A method for activating electrochemical cells including the steps of sealing the electrochemical cells in a container with an activating electrolyte solvent and salt, treatment steps, such as the application of compression and decompression cycles to the container, for providing good distribution of the electrolyte within the electrochemical cells.
摘要翻译： 一种激活电化学电池的方法，包括用活化电解质溶剂和盐密封容器中的电化学电池的步骤，处理步骤，例如向容器施加压缩和减压循环，以提供电解质在该容器内的良好分布 电化学电池。
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公开(公告)号：US4433036A
公开(公告)日：1984-02-21
申请号：US364105
申请日：1982-03-31
CPC分类号： H01M6/38
摘要： A reserve battery having a plurality of galvanic cells and a series of ports through which electrolyte can flow into the cells. A spring activated valve opens the ports during periods of angular acceleration of the battery and closes the ports when there is no acceleration.
摘要翻译： 一种备用电池，具有多个电池单元和一系列端口，电解液可以通过这些端口流入电池。 弹簧启动阀在电池角加速期间打开端口，并且当没有加速时关闭端口。
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9.发明授权Stabilization of LiAsF.sub.6 /dimethyl sulfite electrolyte solution 失效稳定LiAsF {HD 6 {B /二甲基亚硫酸盐电解质溶液
公开(公告)号：US4107404A
公开(公告)日：1978-08-15
申请号：US833401
申请日：1977-09-15
申请人： Robert J. Horning , Walter B. Ebner
发明人： Robert J. Horning , Walter B. Ebner
摘要： LiAsF.sub.6 /dimethyl sulfite electrolyte solutions of improved storage sility are obtained by incorporating metallic lithium therein.
摘要翻译： 通过在其中加入金属锂可以获得提高储存稳定性的LiAsF6 /二甲基亚硫酸盐电解质溶液。
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