公开(公告)号：US20130194869A1

公开(公告)日：2013-08-01

申请号：US13605942

申请日：2012-09-06

申请人： Eun Seok CHOI ,  Jung Ryul Ahn ,  Se Hoon Kim ,  Young Dae Park ,  In Geun Lim ,  Jung Seok Oh

发明人： Eun Seok CHOI ,  Jung Ryul Ahn ,  Se Hoon Kim ,  Young Dae Park ,  In Geun Lim ,  Jung Seok Oh

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/11565 ,  H01L27/11582

摘要： A three-dimensional (3-D) non-volatile memory device according to embodiment of the present invention includes a plurality of bit lines, at least one string row extending in a first direction coupled to the bit lines and including 2N strings, wherein the N includes a natural number, a common source selection line configured to control source selection transistors of the 2N strings included in a memory block, a first common drain selection line configured to control drain selection transistors of a first string and a 2N-th string among the 2N strings included in a memory block, and N−1 second common drain selection lines configured to control drain selection transistors of adjacent strings in the first direction among remaining strings other than the first string and the 2N-th string.

摘要翻译： 根据本发明的实施例的三维（3-D）非易失性存储器件包括多个位线，至少一个串行沿第一方向延伸，耦合到位线并包括2N个字符串，其中， N包括自然数，被配置为控制包括在存储块中的2N串的源选择晶体管的公共源选择线，被配置为控制第一串的漏极选择晶体管和第2N串的第2N串的第一公共漏极选择线 包括在存储块中的2N个串，以及N-1个第二公共漏极选择线，被配置为控制除第一串和第2N个串之外的剩余串之中的第一方向上的相邻串的漏极选择晶体管。

公开(公告)号：US08743612B2

公开(公告)日：2014-06-03

申请号：US13605942

申请日：2012-09-06

申请人： Eun Seok Choi ,  Jung Ryul Ahn ,  Se Hoon Kim ,  Yong Dae Park ,  In Geun Lim ,  Jung Seok Oh

发明人： Eun Seok Choi ,  Jung Ryul Ahn ,  Se Hoon Kim ,  Yong Dae Park ,  In Geun Lim ,  Jung Seok Oh

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/11565 ,  H01L27/11582

摘要： A three-dimensional (3-D) non-volatile memory device according to embodiment of the present invention includes a plurality of bit lines, at least one string row extending in a first direction coupled to the bit lines and including 2N strings, wherein the N includes a natural number, a common source selection line configured to control source selection transistors of the 2N strings included in a memory block, a first common drain selection line configured to control drain selection transistors of a first string and a 2N-th string among the 2N strings included in a memory block, and N−1 second common drain selection lines configured to control drain selection transistors of adjacent strings in the first direction among remaining strings other than the first string and the 2N-th string.

摘要翻译： 根据本发明的实施例的三维（3-D）非易失性存储器件包括多个位线，至少一个串行沿第一方向延伸，耦合到位线并包括2N个字符串，其中， N包括自然数，被配置为控制包括在存储块中的2N串的源选择晶体管的公共源选择线，被配置为控制第一串的漏极选择晶体管和第2N串的第2N串的第一公共漏极选择线 包括在存储块中的2N个串，以及N-1个第二公共漏极选择线，被配置为控制除第一串和第2N个串之外的剩余串之中的第一方向上的相邻串的漏极选择晶体管。

公开(公告)号：US07955960B2

公开(公告)日：2011-06-07

申请号：US12052914

申请日：2008-03-21

申请人： Se Jun Kim ,  Eun Seok Choi ,  Kyoung Hwan Park ,  Hyun Seung Yoo ,  Myung Shik Lee ,  Young Ok Hong ,  Jung Ryul Ahn ,  Yong Top Kim ,  Kyung Pil Hwang ,  Won Sic Woo ,  Jae Young Park ,  Ki Hong Lee ,  Ki Seon Park ,  Moon Sig Joo

发明人： Se Jun Kim ,  Eun Seok Choi ,  Kyoung Hwan Park ,  Hyun Seung Yoo ,  Myung Shik Lee ,  Young Ok Hong ,  Jung Ryul Ahn ,  Yong Top Kim ,  Kyung Pil Hwang ,  Won Sic Woo ,  Jae Young Park ,  Ki Hong Lee ,  Ki Seon Park ,  Moon Sig Joo

IPC分类号： H01L21/336

CPC分类号： H01L29/513 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/792

摘要： A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.

摘要翻译： 提供了一种非易失性存储器件及其制造方法，以防止存储在电荷陷阱层中的电荷移动到相邻存储器单元。 制造非易失性存储器件的方法包括在半导体衬底上形成第一电介质层，其中有源区由隔离层限定，在第一电介质层上形成电荷陷阱层，去除第一介电层和电荷陷阱层 在隔离层上，在包括电荷陷阱层的隔离层上形成第二电介质层，并在第二介电层上形成导电层。

公开(公告)号：US08111557B2

公开(公告)日：2012-02-07

申请号：US12647586

申请日：2009-12-28

申请人： Jung Ryul Ahn

发明人： Jung Ryul Ahn

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A nonvolatile memory device and a method of programming the device includes storing first data in first main and sub-registers and storing second data in second main and sub-registers, performing first program and verification operations on first memory cells based on the first data stored in the first main register, storing a result of the first verification operation in the first main register, performing a second program operation on second memory cells based on the second data stored in the second main register, changing the result of the first verification operation, stored in the first main register, into the first data stored in the first sub-register, performing an additional verification operation on the first memory cells on which the first verification operation has been completed, storing a result of the additional verification operation in the first main register, and performing a second verification operation on the second memory cells.

摘要翻译： 非易失性存储器件和编程器件的方法包括：将第一数据存储在第一主存储器和子寄存器中，并将第二数据存储在第二主寄存器和子寄存器中，基于存储的第一数据对第一存储器单元执行第一程序和验证操作 在第一主寄存器中，将第一验证操作的结果存储在第一主寄存器中，基于存储在第二主寄存器中的第二数据对第二存储器单元执行第二编程操作，改变第一验证操作的结果， 存储在第一主寄存器中的第一存储单元中的第一数据存储在第一子寄存器中，对已经完成了第一验证操作的第一存储单元执行附加验证操作，将附加验证操作的结果存储在第一主寄存器中 主寄存器，并对第二存储单元执行第二验证操作。

公开(公告)号：US20100246273A1

公开(公告)日：2010-09-30

申请号：US12647586

申请日：2009-12-28

申请人： Jung Ryul Ahn

发明人： Jung Ryul Ahn

IPC分类号： G11C16/06 ,  G11C7/10

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A nonvolatile memory device and a method of programming the device includes storing first data in first main and sub-registers and storing second data in second main and sub-registers, performing first program and verification operations on first memory cells based on the first data stored in the first main register, storing a result of the first verification operation in the first main register, performing a second program operation on second memory cells based on the second data stored in the second main register, changing the result of the first verification operation, stored in the first main register, into the first data stored in the first sub-register, performing an additional verification operation on the first memory cells on which the first verification operation has been completed, storing a result of the additional verification operation in the first main register, and performing a second verification operation on the second memory cells.

摘要翻译： 非易失性存储器件和编程器件的方法包括：将第一数据存储在第一主存储器和子寄存器中，并将第二数据存储在第二主寄存器和子寄存器中，基于存储的第一数据对第一存储器单元执行第一程序和验证操作 在第一主寄存器中，将第一验证操作的结果存储在第一主寄存器中，基于存储在第二主寄存器中的第二数据对第二存储器单元执行第二编程操作，改变第一验证操作的结果， 存储在第一主寄存器中的第一存储单元中的第一数据存储在第一子寄存器中，对已经完成了第一验证操作的第一存储单元执行附加验证操作，将附加验证操作的结果存储在第一主寄存器中 主寄存器，并对第二存储单元执行第二验证操作。

公开(公告)号：US07662697B2

公开(公告)日：2010-02-16

申请号：US11416738

申请日：2006-05-02

申请人： Jung Ryul Ahn ,  Byung Soo Park

发明人： Jung Ryul Ahn ,  Byung Soo Park

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： A method of forming a semiconductor device includes etching a semiconductor substrate to form a first trench having a first width and a first depth; etching the semiconductor substrate to form a second trench having a second width and a second depth, the second trench overlapping the first trench, the second width being greater than the first width, the second depth being less than the first depth, whereby a trench having a dual structure is formed; and forming a first isolation structure within the trench having the dual structure. An embodiment of the present invention relates to a method of forming an isolation structure of a semiconductor device.

摘要翻译： 形成半导体器件的方法包括蚀刻半导体衬底以形成具有第一宽度和第一深度的第一沟槽; 蚀刻所述半导体衬底以形成具有第二宽度和第二深度的第二沟槽，所述第二沟槽与所述第一沟槽重叠，所述第二宽度大于所述第一宽度，所述第二深度小于所述第一深度，由此具有 形成双重结构; 以及在具有双重结构的沟槽内形成第一隔离结构。 本发明的实施例涉及一种形成半导体器件的隔离结构的方法。

公开(公告)号：US06759299B2

公开(公告)日：2004-07-06

申请号：US10321720

申请日：2002-12-18

申请人： Young Bok Lee ,  Sung Mun Jung ,  Jung Ryul Ahn

发明人： Young Bok Lee ,  Sung Mun Jung ,  Jung Ryul Ahn

IPC分类号： H01L218247

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： The present invention relates to a method of manufacturing a flash memory device. In the method, a low-voltage transistor is formed to have a DDD structure same to a high-voltage transistor when a peripheral region is formed in the manufacture process of the flash memory device. As the process for forming the LDD structure for the low voltage is omitted, the cost is reduced in the entire process of manufacturing the flash memory device. Also, as the junction breakdown voltage of the low-voltage transistor is increased and current is increased, the device characteristics is improved

摘要翻译： 本发明涉及一种制造闪速存储器件的方法。 在该方法中，当在闪速存储器件的制造过程中形成周边区域时，形成低压晶体管，以使DDD结构与高电压晶体管相同。 由于省略了用于形成用于低电压的LDD结构的工艺，所以在制造闪存器件的整个过程中降低了成本。 此外，随着低压晶体管的结击穿电压增加并且电流增加，器件特性得到改善

公开(公告)号：US08351270B2

公开(公告)日：2013-01-08

申请号：US13344349

申请日：2012-01-05

申请人： Jung Ryul Ahn

发明人： Jung Ryul Ahn

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A nonvolatile memory device and a method of programming the device includes storing first data in first main and sub-registers and storing second data in second main and sub-registers, performing first program and verification operations on first memory cells based on the first data stored in the first main register, storing a result of the first verification operation in the first main register, performing a second program operation on second memory cells based on the second data stored in the second main register, changing the result of the first verification operation, stored in the first main register, into the first data stored in the first sub-register, performing an additional verification operation on the first memory cells on which the first verification operation has been completed, storing a result of the additional verification operation in the first main register, and performing a second verification operation on the second memory cells.

摘要翻译： 非易失性存储器件和编程器件的方法包括：将第一数据存储在第一主存储器和子寄存器中，并将第二数据存储在第二主寄存器和子寄存器中，基于存储的第一数据对第一存储器单元执行第一程序和验证操作 在第一主寄存器中，将第一验证操作的结果存储在第一主寄存器中，基于存储在第二主寄存器中的第二数据对第二存储器单元执行第二编程操作，改变第一验证操作的结果， 存储在第一主寄存器中的第一存储单元中的第一数据存储在第一子寄存器中，对已经完成了第一验证操作的第一存储单元执行附加验证操作，将附加验证操作的结果存储在第一主寄存器中 主寄存器，并对第二存储单元执行第二验证操作。

公开(公告)号：US07169670B2

公开(公告)日：2007-01-30

申请号：US10880691

申请日：2004-06-30

申请人： Min Kyu Lee ,  Hee Hyun Chang ,  Jum Soo Kim ,  Jung Ryul Ahn

发明人： Min Kyu Lee ,  Hee Hyun Chang ,  Jum Soo Kim ,  Jung Ryul Ahn

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/11534 ,  Y10S438/981

摘要： Provided is related to a method of forming a semiconductor device comprises steps of: providing a semiconductor substrate having a low voltage region and a high voltage region; forming a pad oxide layer and a pad nitride layer in sequence on the semiconductor substrate; removing the pad nitride layer and the pad oxide layer on the semiconductor substrate of the high voltage region, wherein a surface of the semiconductor substrate of the high voltage region is exposed and recessed; forming a sacrificial oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the sacrificial layer; forming a first gate oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the pad oxide layer and the pad nitride layer left on the semiconductor substrate of the low voltage region, wherein a surface of the semiconductor substrate of the low voltage region is exposed and recessed; and forming a second gate oxide layer on the first gate oxide layer and the surface of the semiconductor substrate of the low voltage region.

摘要翻译： 提供一种形成半导体器件的方法，包括以下步骤：提供具有低电压区域和高电压区域的半导体衬底; 在半导体衬底上依次形成焊盘氧化物层和焊盘氮化物层; 去除高电压区域的半导体衬底上的衬垫氮化物层和衬垫氧化物层，其中高压区域的半导体衬底的表面被暴露和凹陷; 在高电压区域的半导体衬底的表面上形成牺牲氧化物层; 去除牺牲层; 在所述高电压区域的半导体衬底的表面上形成第一栅氧化层; 去除低电压区域的半导体衬底上留下的衬垫氧化物层和衬垫氮化物层，其中低电压区域的半导体衬底的表面露出并凹陷; 以及在所述第一栅极氧化物层和所述低电压区域的所述半导体衬底的表面上形成第二栅极氧化物层。

公开(公告)号：US20070155124A1

公开(公告)日：2007-07-05

申请号：US11593868

申请日：2006-11-07

申请人： Jung Ryul Ahn ,  Jum Soo Kim

发明人： Jung Ryul Ahn ,  Jum Soo Kim

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  H01L27/1052

摘要： A method of manufacturing a semiconductor device wherein a gate insulating layer and a polysilicon layer are formed over a semiconductor substrate in which a cell region and a peri region are defined. Portions of the polysilicon layer, the gate insulating layer, and the semiconductor substrate of the peri region are etched to form a first trench in the peri region. A first insulating layer is formed on the entire surface so that the first trench is gap filled. Portions of the first insulating layer, the first polysilicon layer, the gate insulating layer, and the semiconductor substrate of the cell region are etched to form second trenches in the cell region. A sidewall oxide layer and a nitride layer are formed within the second trenches, so that the sidewall oxide layer and the nitride layer are laminated. The second trenches are gap-filled with a second insulating layer to form isolation layers. Since plasma attack and the infiltration of hydrogen (H2) can be prevented, the malfunction of a cell and peripheral circuits can be prevented.

摘要翻译： 一种半导体器件的制造方法，其中在限定了单元区域和周边区域的半导体衬底上形成栅极绝缘层和多晶硅层。 蚀刻多晶硅层的一部分，栅极绝缘层和半导体衬底，以在周边区域形成第一沟槽。 在整个表面上形成第一绝缘层，使得第一沟槽间隙填充。 蚀刻单元区域的第一绝缘层，第一多晶硅层，栅极绝缘层和半导体衬底的部分，以在单元区域中形成第二沟槽。 在第二沟槽内形成侧壁氧化物层和氮化物层，从而层叠侧壁氧化物层和氮化物层。 第二沟槽间隙填充有第二绝缘层以形成隔离层。 由于可以防止等离子体侵蚀和氢（H 2 2）的渗透，所以可以防止电池和外围电路的故障。