公开(公告)号：US08077268B2

公开(公告)日：2011-12-13

申请号：US12140655

申请日：2008-06-17

申请人： Eun-Guk Lee ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Do-Hyun Kim ,  Soon-Kwon Lim

发明人： Eun-Guk Lee ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Do-Hyun Kim ,  Soon-Kwon Lim

IPC分类号： G02F1/13

CPC分类号： H01L27/1225 ,  H01L29/7869

摘要： A thin film transistor array substrate comprising a base substrate, a first wire on the base substrate, a first insulating layer on the base substrate to cover the first wire, a semiconductor layer on the first insulating layer, a second insulating layer on the first insulating layer on which the semiconductor layer is formed, and a second wire on the second insulating layer on the second insulating layer is provided, and a portion of the second wire makes contact with the semiconductor layer through the contact hole.

摘要翻译： 一种薄膜晶体管阵列基板，包括基底基板，在基底基板上的第一布线，在基底基板上覆盖第一布线的第一绝缘层，第一绝缘层上的半导体层，第一绝缘层上的第二绝缘层 设置有半导体层的层，第二绝缘层上的第二绝缘层上的第二布线，第二布线的一部分通过接触孔与半导体层接触。

公开(公告)号：US20080142797A1

公开(公告)日：2008-06-19

申请号：US12001031

申请日：2007-12-06

申请人： Eun-Guk Lee ,  Do-Hyun Kim ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Soon-Kwon Lim

发明人： Eun-Guk Lee ,  Do-Hyun Kim ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Soon-Kwon Lim

IPC分类号： H01L29/22 ,  H01L21/84

CPC分类号： H01L27/124 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/7869

摘要： A thin film transistor substrate and a method of manufacturing the same are disclosed. The method of manufacturing a thin film transistor substrate includes forming a first conductive pattern group including a gate line, a gate electrode, and a lower gate pad electrode on a substrate, forming a gate insulating layer on the substrate on which the first conductive pattern group is formed, forming an oxide semiconductor pattern overlapping the gate electrode on the gate insulating layer, and forming first and second conductive layers on the substrate on which the oxide semiconductor pattern is formed and patterning the first and second conductive layers to form a second conductive pattern group including a data line, a source electrode, a drain electrode, and a data pad.

摘要翻译： 公开了一种薄膜晶体管基板及其制造方法。 制造薄膜晶体管基板的方法包括在基板上形成包括栅极线，栅电极和下栅极焊盘电极的第一导电图案组，在基板上形成栅极绝缘层，第一导电图案组 形成，在所述栅极绝缘层上形成与所述栅电极重叠的氧化物半导体图案，以及在其上形成有所述氧化物半导体图案的所述基板上形成第一和第二导电层，并且对所述第一导电层和所述第二导电层进行构图以形成第二导电图案 包括数据线，源电极，漏电极和数据焊盘。

公开(公告)号：US07923287B2

公开(公告)日：2011-04-12

申请号：US12001031

申请日：2007-12-06

申请人： Eun-Guk Lee ,  Do-Hyun Kim ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Soon-Kwon Lim

发明人： Eun-Guk Lee ,  Do-Hyun Kim ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Soon-Kwon Lim

IPC分类号： H01L21/84 ,  H01L29/786

CPC分类号： H01L27/124 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/7869

摘要： A thin film transistor substrate and a method of manufacturing the same are disclosed. The method of manufacturing a thin film transistor substrate includes forming a first conductive pattern group including a gate line, a gate electrode, and a lower gate pad electrode on a substrate, forming a gate insulating layer on the substrate on which the first conductive pattern group is formed, forming an oxide semiconductor pattern overlapping the gate electrode on the gate insulating layer, and forming first and second conductive layers on the substrate on which the oxide semiconductor pattern is formed and patterning the first and second conductive layers to form a second conductive pattern group including a data line, a source electrode, a drain electrode, and a data pad.

摘要翻译： 公开了一种薄膜晶体管基板及其制造方法。 制造薄膜晶体管基板的方法包括在基板上形成包括栅极线，栅电极和下栅极焊盘电极的第一导电图案组，在基板上形成栅极绝缘层，第一导电图案组 形成，在所述栅极绝缘层上形成与所述栅电极重叠的氧化物半导体图案，以及在其上形成有所述氧化物半导体图案的所述基板上形成第一和第二导电层，并且对所述第一导电层和所述第二导电层进行构图以形成第二导电图案 包括数据线，源电极，漏电极和数据焊盘。

公开(公告)号：US20090026450A1

公开(公告)日：2009-01-29

申请号：US12140655

申请日：2008-06-17

申请人： Eun-Guk LEE ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Do-Hyun Kim ,  Soon-Kwon Lim

发明人： Eun-Guk LEE ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Do-Hyun Kim ,  Soon-Kwon Lim

IPC分类号： H01L23/48 ,  H01L29/04 ,  H01L21/4763

CPC分类号： H01L27/1225 ,  H01L29/7869

摘要： A thin film transistor array substrate comprising a base substrate, a first wire on the base substrate, a first insulating layer on the base substrate to cover the first wire, a semiconductor layer on the first insulating layer, a second insulating layer on the first insulating layer on which the semiconductor layer is formed, and a second wire on the second insulating layer on the second insulating layer is provided, and a portion of the second wire makes contact with the semiconductor layer through the contact hole.

摘要翻译： 一种薄膜晶体管阵列基板，包括基底基板，在基底基板上的第一布线，在基底基板上覆盖第一布线的第一绝缘层，第一绝缘层上的半导体层，第一绝缘层上的第二绝缘层 设置有半导体层的层，第二绝缘层上的第二绝缘层上的第二配线，第二配线的一部分通过接触孔与半导体层接触。

公开(公告)号：US07919795B2

公开(公告)日：2011-04-05

申请号：US11961149

申请日：2007-12-20

申请人： Je-Hun Lee ,  Chang-Oh Jeong ,  Eun-Guk Lee ,  Do-Hyun Kim

发明人： Je-Hun Lee ,  Chang-Oh Jeong ,  Eun-Guk Lee ,  Do-Hyun Kim

IPC分类号： H01L29/76 ,  H01L29/40 ,  H01L29/43 ,  H01L29/49 ,  H01L33/00

CPC分类号： H01L29/458 ,  H01L27/124 ,  H01L29/4908

摘要： Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper, copper solid solution layer.

摘要翻译： 提供线结构，制造线的方法，薄膜晶体管（TFT）基板和制造TFT基板的方法。 导线结构包括形成在基板上并包括铜，铜固溶体层的阻挡层。

公开(公告)号：US20080203390A1

公开(公告)日：2008-08-28

申请号：US11932233

申请日：2007-10-31

申请人： Do-Hyun Kim ,  Won-Suk Shin ,  Chang-Oh Jeong ,  Hong-Sick Park ,  Eun-Guk Lee ,  Je-Hun Lee

发明人： Do-Hyun Kim ,  Won-Suk Shin ,  Chang-Oh Jeong ,  Hong-Sick Park ,  Eun-Guk Lee ,  Je-Hun Lee

IPC分类号： H01L29/49 ,  H01L21/44 ,  H01L21/84

CPC分类号： H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458

摘要： A method for manufacturing a thin film transistor array panel includes forming a gate line on a substrate; sequentially forming a gate insulating layer, a silicon layer, and a conductor layer including a lower layer and an upper layer on the gate line, forming a photoresist film, on the conductor layer, patterning the photoresist film to form a photoresist pattern including a first portion and a second portion having a greater thickness than the first portion, etching the upper layer and the lower layer by using the photoresist pattern as art etch mask, etching the silicon layer by using the photoresist pattern as an etch mask to form a semiconductor, removing the second portion of the photoresist pattern by using an etch back process, selectively wet-etching the upper layer of the conductor layer by using the photoresist pattern as an etch mask, dry-etching the lower layer of the conductor layer by using the photoresist pattern as an etch mask to form a data line and a drain electrode including remaining upper and lower layers, and forming a pixel electrode connected to the drain electrode.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法，包括在基板上形成栅极线; 在栅极线上顺序地形成栅极绝缘层，硅层和包括下层和上层的导体层，在导体层上形成光致抗蚀剂膜，图案化光致抗蚀剂膜以形成包括第一 部分和第二部分具有比第一部分更大的厚度，通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻上层和下层，通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻硅层以形成半导体， 通过使用回蚀工艺去除光致抗蚀剂图案的第二部分，通过使用光致抗蚀剂图案作为蚀刻掩模来选择性地湿法蚀刻导体层的上层，通过使用光致抗蚀剂干蚀刻导体层的下层 图案作为蚀刻掩模以形成包括剩余的上层和下层的数据线和漏极，并且形成连接到漏电极的像素电极 。

公开(公告)号：US08507956B2

公开(公告)日：2013-08-13

申请号：US13051904

申请日：2011-03-18

申请人： Je-Hun Lee ,  Chang-Oh Jeong ,  Eun-Guk Lee ,  Do-Hyun Kim

发明人： Je-Hun Lee ,  Chang-Oh Jeong ,  Eun-Guk Lee ,  Do-Hyun Kim

IPC分类号： H01L33/00 ,  H01L29/43 ,  H01L29/49 ,  H01L29/76

CPC分类号： H01L29/458 ,  H01L27/124 ,  H01L29/4908

摘要： Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including a copper layer and a copper solid solution layer.

摘要翻译： 提供线结构，制造线的方法，薄膜晶体管（TFT）基板和制造TFT基板的方法。 导线结构包括在基板上形成的包含铜层和铜固溶体层的阻挡层。

公开(公告)号：US07811868B2

公开(公告)日：2010-10-12

申请号：US11932233

申请日：2007-10-31

申请人： Do-Hyun Kim ,  Won-Suk Shin ,  Chang-Oh Jeong ,  Hong-Sick Park ,  Eun-Guk Lee ,  Je-Hun Lee

发明人： Do-Hyun Kim ,  Won-Suk Shin ,  Chang-Oh Jeong ,  Hong-Sick Park ,  Eun-Guk Lee ,  Je-Hun Lee

IPC分类号： H01L21/768

CPC分类号： H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458

摘要： A method for manufacturing a thin film transistor array panel includes forming a gate line on a substrate; sequentially forming a gate insulating layer, a silicon layer, and a conductor layer including a lower layer and an upper layer on the gate line, forming a photoresist film, on the conductor layer, patterning the photoresist film to form a photoresist pattern including a first portion and a second portion having a greater thickness than the first portion, etching the upper layer and the lower layer by using the photoresist pattern as art etch mask, etching the silicon layer by using the photoresist pattern as an etch mask to form a semiconductor, removing the second portion of the photoresist pattern by using an etch back process, selectively wet-etching the upper layer of the conductor layer by using the photoresist pattern as an etch mask, dry-etching the lower layer of the conductor layer by using the photoresist pattern as an etch mask to form a data line and a drain electrode including remaining upper and lower layers, and forming a pixel electrode connected to the drain electrode.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法，包括在基板上形成栅极线; 在栅极线上顺序地形成栅极绝缘层，硅层和包括下层和上层的导体层，在导体层上形成光致抗蚀剂膜，图案化光致抗蚀剂膜以形成包括第一 部分和第二部分具有比第一部分更大的厚度，通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻上层和下层，通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻硅层以形成半导体， 通过使用回蚀工艺去除光致抗蚀剂图案的第二部分，通过使用光致抗蚀剂图案作为蚀刻掩模来选择性地湿法蚀刻导体层的上层，通过使用光致抗蚀剂干蚀刻导体层的下层 图案作为蚀刻掩模以形成包括剩余的上层和下层的数据线和漏极，并且形成连接到漏电极的像素电极 。

公开(公告)号：US08946005B2

公开(公告)日：2015-02-03

申请号：US13030213

申请日：2011-02-18

申请人： Je-Hun Lee ,  Do-Hyun Kim ,  Eun-Guk Lee ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Do-Hyun Kim ,  Eun-Guk Lee ,  Chang-Oh Jeong

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L29/786 ,  H01L27/12

CPC分类号： H01L29/7869 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288

摘要： A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.

摘要翻译： 薄膜晶体管包括半导体图案，源极和漏极以及栅极，半导体图案形成在基底基板上，半导体图案包括金属氧化物。 源极和漏极形成在半导体图案上，使得源极和漏极彼此间隔开，并且源极和漏极的轮廓与半导体图案的轮廓基本相同。 栅电极设置在源电极和漏电极之间的区域中，使得栅电极的一部分与源电极和漏电极重叠。 因此，由光引起的漏电流最小化。 结果，增强了薄膜晶体管的特性，减少了后图像以提高显示质量，并且提高了制造工艺的稳定性。

公开(公告)号：US20090162982A1

公开(公告)日：2009-06-25

申请号：US12392629

申请日：2009-02-25

申请人： Je-Hun Lee ,  Do-Hyun Kim ,  Eun-Guk Lee ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Do-Hyun Kim ,  Eun-Guk Lee ,  Chang-Oh Jeong

IPC分类号： H01L21/336

CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/124

摘要： An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is disposed on the insulating substrate. The conductive line is disposed on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and has a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is disposed on the insulating substrate, and is connected to the drain electrode of the switching element through the contact hole.

摘要翻译： 阵列基板包括开关元件，信号传输线，钝化层和像素电极。 开关元件设置在绝缘基板上。 信号传输线连接到开关元件，并且包括阻挡层，导电线和氮化铜层。 阻挡层设置在绝缘基板上。 导电线设置在阻挡层上并且包括铜或铜合金。 氮化铜层覆盖导电线。 钝化层覆盖开关元件和信号传输线，并且具有接触孔，开关元件的漏电极通过该接触孔部分露出。 像素电极设置在绝缘基板上，并通过接触孔与开关元件的漏电极连接。