公开(公告)号：US06528841B2

公开(公告)日：2003-03-04

申请号：US09995501

申请日：2001-11-26

申请人： Eun-Young Choi ,  Jung-Dal Choi ,  Jae-Duk Lee ,  Hong-Soo Kim

发明人： Eun-Young Choi ,  Jung-Dal Choi ,  Jae-Duk Lee ,  Hong-Soo Kim

IPC分类号： H01L29788

CPC分类号： H01L27/115

摘要： A NAND type flash memory device has a dummy region forming a dummy pattern. In the flash memory device, a common source line is formed to cross only with an isolation layer adjacent an active region of a normal pattern forming memory cells.

公开(公告)号：US20060124988A1

公开(公告)日：2006-06-15

申请号：US11291142

申请日：2005-11-30

申请人： Sung-Hoi Hur ,  Jung-Dal Choi ,  Kyeong-Tae Kim ,  Jong-Ho Park ,  Jae-Duk Lee ,  Ki-Nam Kim

发明人： Sung-Hoi Hur ,  Jung-Dal Choi ,  Kyeong-Tae Kim ,  Jong-Ho Park ,  Jae-Duk Lee ,  Ki-Nam Kim

IPC分类号： H01L21/82 ,  H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor memory device is fabricated by forming an active region protruding from a semiconductor substrate, forming an isolation layer on the substrate adjacent opposing sidewalls of the active region, and forming a floating gate electrode on a surface of the active region between the opposing sidewalls thereof. The floating gate electrode is formed to extend beyond edges of the surface of the active region onto the isolation layer. A surface of the floating gate electrode adjacent the active region defines a plane, and the isolation layer is confined between the plane and the substrate. A control gate electrode is formed on a surface of the floating gate electrode opposite the active region. The control gate electrode may be formed to extend along sidewalls of the floating gate electrode towards the substrate beyond the plane defined by the surface of the floating gate electrode adjacent the active region. Related devices are also discussed.

摘要翻译： 半导体存储器件通过形成从半导体衬底突出的有源区域形成，在邻近有源区域的相对侧壁的衬底上形成隔离层，以及在其相对侧壁之间的有源区域的表面上形成浮栅电极 。 浮栅电极被形成为延伸超过有源区表面的边缘到隔离层上。 邻近有源区的浮栅电极的表面限定了一个平面，隔离层被限制在平面和衬底之间。 控制栅电极形成在浮动栅电极的与有源区相对的表面上。 控制栅电极可以被形成为沿着浮置栅电极的侧壁朝着衬底延伸超过由邻近有源区的浮栅的表面限定的平面。 还讨论了相关设备。

公开(公告)号：US06979628B2

公开(公告)日：2005-12-27

申请号：US10726788

申请日：2003-12-02

申请人： Hong-Soo Kim ,  Kyu-Charn Park ,  Jung-Dal Choi ,  Seong-Soon Cho

发明人： Hong-Soo Kim ,  Kyu-Charn Park ,  Jung-Dal Choi ,  Seong-Soon Cho

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/76205 ,  H01L21/76213 ,  H01L21/76232 ,  H01L21/76237

摘要： Semiconductor devices and methods of forming devices that have field oxides in trenches are disclosed. According to the methods, a semiconductor substrate is prepared. An upper trench is formed at a predetermined region of the semiconductor substrate and a bottom trench is formed at a bottom surface of the upper trench. A field oxide is formed to fill the bottom trench and the upper trench. At this time, the upper trench has a wider width than the bottom trench.

摘要翻译： 公开了在沟槽中形成具有场氧化物的器件的半导体器件和方法。 根据该方法制备半导体衬底。 在半导体衬底的预定区域处形成上沟槽，并且在上沟槽的底表面处形成底沟槽。 形成场氧化物以填充底部沟槽和上部沟槽。 此时，上沟槽的宽度比底沟宽。

公开(公告)号：US06828637B2

公开(公告)日：2004-12-07

申请号：US10794533

申请日：2004-03-05

申请人： Hong-Soo Kim ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yong-Joon Choi

发明人： Hong-Soo Kim ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yong-Joon Choi

IPC分类号： H01L2976

CPC分类号： H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device having a dummy active region is provided, which includes a plurality of parallel main active regions and a dummy active region coupled to ends of the main active regions. The main preferably active regions are arranged in a main memory cell array region and extend to or through a dummy cell array region surrounding the main memory cell array region. Further, the dummy active region is perpendicular to the main active regions. A redundancy cell array region may intervene between the main memory cell array region and the dummy cell array region. In this case, the main active regions are extended to the dummy cell array region through the redundancy cell array region.

摘要翻译： 提供了具有虚设有源区的半导体存储器件，其包括多个平行的主有效区和与主有效区的端部耦合的虚拟有源区。 主要优选的有源区域被布置在主存储单元阵列区域中并且延伸到或通过围绕主存储单元阵列区域的虚设单元阵列区域。 此外，虚拟有源区域垂直于主要有源区域。 冗余单元阵列区域可以介于主存储单元阵列区域和虚设单元阵列区域之间。 在这种情况下，主要有源区域通过冗余单元阵列区域扩展到虚拟单元阵列区域。

公开(公告)号：US07084440B2

公开(公告)日：2006-08-01

申请号：US10376465

申请日：2003-02-28

申请人： Jong-Sun Sel ,  Hong-Soo Kim ,  Jung-Dal Choi

发明人： Jong-Sun Sel ,  Hong-Soo Kim ,  Jung-Dal Choi

IPC分类号： H01L27/10 ,  H01L29/73 ,  H01L23/58 ,  H01L29/76

CPC分类号： H01L27/0207 ,  H01L27/115

摘要： An integrated circuit layout and a semiconductor device manufactured using the same are provided. According to one embodiment, a semiconductor device has a substrate and a plurality of bar type patterns on the substrate. The bar type patterns are substantially parallel to each other. At least one of the bar type patterns includes first and second ends and a middle part therebetween. The bar type patterns has an overhang at the first end thereof. The bar type patterns may be gate patterns, bit line patterns or active patterns.

公开(公告)号：US06806518B2

公开(公告)日：2004-10-19

申请号：US10794508

申请日：2004-03-05

申请人： Hong-Soo Kim ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yong-Joon Choi

发明人： Hong-Soo Kim ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yong-Joon Choi

IPC分类号： H01L2710

CPC分类号： H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device having a dummy active region is provided, which includes a plurality of parallel main active regions and a dummy active region coupled to ends of the main active regions. The main preferably active regions are arranged in a main memory cell array region and extend to or through a dummy cell array region surrounding the main memory cell array region. Further, the dummy active region is perpendicular to the main active regions. A redundancy cell array region may intervene between the main memory cell array region and the dummy cell array region. In this case, the main active regions are extended to the dummy cell array region through the redundancy cell array region.

公开(公告)号：US07508048B2

公开(公告)日：2009-03-24

申请号：US10758802

申请日：2004-01-15

申请人： Dae-Woong Kang ,  Hong-Soo Kim ,  Jung-Dal Choi ,  Kyu-Charn Park ,  Seong-Soon Cho ,  Yong-Sik Yim ,  Sung-Nam Chang

发明人： Dae-Woong Kang ,  Hong-Soo Kim ,  Jung-Dal Choi ,  Kyu-Charn Park ,  Seong-Soon Cho ,  Yong-Sik Yim ,  Sung-Nam Chang

IPC分类号： H01L29/00

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11543

摘要： Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region. Accordingly, it can minimize a depth of recessed regions (dent regions) to be formed at edge regions of the first isolation layer during removal of the pad insulation layer, and it can prevent dent regions from being formed at edge regions of the second isolation layer.

摘要翻译： 提供了制造具有多栅极绝缘层的半导体器件和由此制造的半导体器件的方法。 该方法包括分别在半导体衬底的第一区域和第二区域上形成衬垫绝缘层和初始高电压栅极绝缘层。 初始高压栅绝缘层形成为比焊垫绝缘层厚。 形成穿过焊盘绝缘层并被埋在半导体衬底中的第一隔离层，以限定第一区域中的第一有源区和穿过初始高电压栅极绝缘层并被埋在半导体中的第二隔离层 形成衬底以限定第二区域中的第二有源区。 然后去除焊盘绝缘层以露出第一有源区。 在暴露的第一有源区上形成低压栅极绝缘层。 因此，能够最大限度地减少在去除焊盘绝缘层期间在第一隔离层的边缘区域形成的凹陷区域（凹陷区域）的深度，并且可以防止凹陷区域形成在第二隔离层的边缘区域 。

公开(公告)号：US06740940B2

公开(公告)日：2004-05-25

申请号：US10135947

申请日：2002-04-29

申请人： Hong-Soo Kim ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yong-Joon Choi

发明人： Hong-Soo Kim ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yong-Joon Choi

IPC分类号： H01L2976

CPC分类号： H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device having a dummy active region is provided, which includes a plurality of parallel main active regions and a dummy active region coupled to ends of the main active regions. The main preferably active regions are arranged in a main memory cell array region and extend to or through a dummy cell array region surrounding the main memory cell array region. Further, the dummy active region is perpendicular to the main active regions. A redundancy cell array region may intervene between the main memory cell array region and the dummy cell array region. In this case, the main active regions are extended to the dummy cell array region through the redundancy cell array region.

公开(公告)号：US20150214478A1

公开(公告)日：2015-07-30

申请号：US14457439

申请日：2014-08-12

申请人： Jung-Moo Lee ,  Youn-Seon Kang ,  Seung-Jae Jung ,  Jung-Dal Choi

发明人： Jung-Moo Lee ,  Youn-Seon Kang ,  Seung-Jae Jung ,  Jung-Dal Choi

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1675

摘要： A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.

摘要翻译： 可变电阻存储器件包括多个第一导线，多个第二导线，多个存储单元，多个第一气隙和多个第二气隙。 第一导线沿第一方向延伸。 第二导线在第一导线上方并且沿与第一方向交叉的第二方向延伸。 存储单元包括可变电阻器件。 存储单元位于第一导线和第二导线的交叉区域。 第一气隙在存储单元之间沿第一方向延伸。 第二气隙沿第二方向在存储单元之间延伸。

公开(公告)号：US08629489B2

公开(公告)日：2014-01-14

申请号：US13357350

申请日：2012-01-24

申请人： Chang-Hyun Lee ,  Jung-Dal Choi

发明人： Chang-Hyun Lee ,  Jung-Dal Choi

IPC分类号： H01L29/76

CPC分类号： H01L27/1052 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.

摘要翻译： 非易失性存储器件包括串选择晶体管，多个存储单元晶体管和与串选择晶体管和多个存储单元晶体管串联电连接的接地选择晶体管。 在存储单元晶体管的沟道和源极/漏极区的边界处形成第一杂质层。 相对于存储单元晶体管的源/漏区，第一杂质层掺杂有相反导电类型的杂质。 第二杂质层形成在串选择晶体管的沟道和漏极区之间的边界处，并且在地选择晶体管的沟道和源极区之间形成。 第二杂质层掺杂有与第一杂质层相同的导电类型杂质，并且具有比第一杂质层更高的杂质浓度。