公开(公告)号：US07689941B1

公开(公告)日：2010-03-30

申请号：US11803091

申请日：2007-05-11

申请人： Teng Chow Ooi ,  Yanzhong Xu ,  Jeffrey T. Watt ,  Haiming Yu

发明人： Teng Chow Ooi ,  Yanzhong Xu ,  Jeffrey T. Watt ,  Haiming Yu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/82

摘要： Systems and methods are provided for computing write margins for dual-port memory. A design for a dual-port memory array cell is generated using a circuit design tool. A user modifies the design of the dual-port memory array cell to incorporate two voltage sources. The voltage sources are used to represent differential noise on the memory cell. A write margin calculation tool uses a circuit simulation tool to perform transient simulations of write-during-read operations on the modified dual-port memory array cell. During the transient simulations, the voltage level on the voltages sources is systematically varied. The write margin for the dual-port memory is determined by analyzing the results of the transient simulations for each of the voltage levels used for the voltage sources.

摘要翻译： 提供了用于计算双端口存储器的写入边距的系统和方法。 使用电路设计工具生成双端口存储器阵列单元的设计。 用户修改双端口存储器阵列单元的设计以并入两个电压源。 电压源用于表示存储单元上的差分噪声。 写余量计算工具使用电路仿真工具对修改后的双端口存储器阵列单元进行写入读取操作的瞬态仿真。 在瞬态模拟期间，电压源上的电压电平有系统地变化。 通过分析用于电压源的每个电压电平的瞬态模拟结果来确定双端口存储器的写入裕度。

公开(公告)号：US20070258313A1

公开(公告)日：2007-11-08

申请号：US11506254

申请日：2006-08-18

申请人： Haiming Yu ,  Tony K. Ngai ,  Kok Heng Choe

发明人： Haiming Yu ,  Tony K. Ngai ,  Kok Heng Choe

IPC分类号： G11C8/00

CPC分类号： G11C7/12 ,  G11C7/04 ,  G11C7/1075 ,  G11C8/16 ,  G11C8/18

摘要： Dual port memory array circuitry is provided that includes bit line voltage clamping circuitry. The clamping circuitry contains control transistors that are used to enable and disable the clamping circuitry. The clamping circuitry also contains voltage regulator transistors and feedback paths. When a write operation is performed on one port of the dual port memory array while a read operation is being performed on the other port of the dual port memory array, the bit line voltage clamping circuitry prevents the voltages on the read port bit lines from dropping too low. This allows the write operation to be performed rapidly, even if the memory cell being written to has been adversely affected by variations due to process, voltage, and temperature.

摘要翻译： 提供了包括位线电压钳位电路的双端口存储器阵列电路。 钳位电路包含用于启用和禁用钳位电路的控制晶体管。 钳位电路还包含稳压晶体管和反馈路径。 当在双端口存储器阵列的另一端口执行读取操作时在双端口存储器阵列的一个端口上执行写入操作时，位线电压钳位电路防止读取端口位线上的电压下降 太低。 即使写入的存储单元受到过程，电压和温度的变化的不利影响，也可以快速执行写入操作。

公开(公告)号：US07289372B1

公开(公告)日：2007-10-30

申请号：US11502817

申请日：2006-08-11

申请人： Haiming Yu ,  Wei Yee Koay

发明人： Haiming Yu ,  Wei Yee Koay

IPC分类号： G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1075 ,  G11C7/1096 ,  G11C8/16

摘要： Dual port memory blocks that have a reduced layout area are provided. The write drivers and sense amplifiers are shared between the dual ports to reduce the number of write drivers and sense amplifiers to save layout area. The write drivers for the two ports are used to write into all of the first port's bitlines. The sense amplifiers for the two ports are used to read from all of the second port's bitlines. A memory block can to support true dual port (TDP) and simple dual port (SDP) operation using substantially less write drivers and sense amplifiers.

摘要翻译： 提供了具有减少的布局面积的双端口存储器块。 写入驱动器和读出放大器在双端口之间共享，以减少写入驱动器和读出放大器的数量，以节省布局面积。 两个端口的写入驱动程序用于写入所有第一个端口的位线。 两个端口的读出放大器用于从所有第二个端口的位线读取。 内存块可以支持真正的双端口（TDP）和简单的双端口（SDP）操作，使用基本上较少的写入驱动器和读出放大器。

公开(公告)号：US07839713B1

公开(公告)日：2010-11-23

申请号：US11897610

申请日：2007-08-31

申请人： Haiming Yu ,  Catherine Chingi Chang

发明人： Haiming Yu ,  Catherine Chingi Chang

IPC分类号： G11C8/00

CPC分类号： G11C5/147 ,  G11C7/1075 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413

摘要： A memory circuit, where data is read from and written to the memory cell in one clock cycle via a port without pre-charging the port between reading data from and writing data to the memory cell via the port in the one clock cycle, is described. In one aspect, an embodiment of the present invention provides a memory circuit with a write control switch that has a voltage drop of substantially zero volts. In another aspect, an embodiment of the present invention provides a memory circuit with a write driver that uses a complementary metal oxide semiconductor (“CMOS”) inverter whose P-channel MOS (“PMOS”) transistor size is approximately 0.5 times its N-channel MOS (“NMOS”) transistor size. In yet another aspect, an embodiment of the present invention provides a memory circuit with a latch-type read sense amplifier.

摘要翻译： 一种存储器电路，其中通过端口以一个时钟周期从存储器单元中读取数据并将其写入存储器单元，而不在一个时钟周期内通过端口从数据读取数据和向存储器单元写入数据之间的端口，而不对端口进行预充电 。 在一个方面，本发明的实施例提供一种具有写入控制开关的存储器电路，其具有基本为零伏特的电压降。 另一方面，本发明的一个实施例提供了一种具有写入驱动器的存储器电路，该写入驱动器使用其P沟道MOS（“PMOS”）晶体管尺寸为其N-型晶体管的大约0.5倍的互补金属氧化物半导体（“CMOS” 通道MOS（“NMOS”）晶体管尺寸。 在另一方面，本发明的实施例提供一种具有锁存型读出放大器的存储电路。

公开(公告)号：USRE41325E1

公开(公告)日：2010-05-11

申请号：US12363461

申请日：2009-01-30

申请人： Haiming Yu ,  Tony K. Ngai ,  Kok Heng Choe

发明人： Haiming Yu ,  Tony K. Ngai ,  Kok Heng Choe

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C7/04 ,  G11C7/1075 ,  G11C8/16 ,  G11C8/18

摘要： Dual port memory array circuitry is provided that includes bit line voltage clamping circuitry. The clamping circuitry contains control transistors that are used to enable and disable the clamping circuitry. The clamping circuitry also contains voltage regulator transistors and feedback paths. When a write operation is performed on one port of the dual port memory array while a read operation is being performed on the other port of the dual port memory array, the bit line voltage clamping circuitry prevents the voltages on the read port bit lines from dropping too low. This allows the write operation to be performed rapidly, even if the memory cell being written to has been adversely affected by variations due to process, voltage, and temperature.

摘要翻译： 提供了包括位线电压钳位电路的双端口存储器阵列电路。 钳位电路包含用于启用和禁用钳位电路的控制晶体管。 钳位电路还包含稳压晶体管和反馈路径。 当在双端口存储器阵列的另一端口执行读取操作时在双端口存储器阵列的一个端口上执行写入操作时，位线电压钳位电路防止读取端口位线上的电压下降 太低。 即使写入的存储单元受到过程，电压和温度的变化的不利影响，也可以快速执行写入操作。

公开(公告)号：US07639557B1

公开(公告)日：2009-12-29

申请号：US11714327

申请日：2007-03-05

申请人： Hao-Yuan Howard Chou ,  Haiming Yu

发明人： Hao-Yuan Howard Chou ,  Haiming Yu

IPC分类号： G11C8/00

CPC分类号： G11C8/16 ,  H03K19/1776 ,  H03K19/1778

摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays that may be configured for true dual port operation or simple dual port operation. The memory arrays include memory cells arranged in rows and columns and associated row address lines and data lines. Sense amplifiers and write drivers are used for reading and writing data. Precharge drivers are used to precharge the data lines prior to read operations. Configurable multiplexer circuitry in the array has read paths through which data is provided to the sense amplifiers from the memory cells. The multiplexer circuitry has write paths through which data from the write drivers is written into the memory cells. The read paths and the write paths contain no more than a single pass gate each. Each precharge driver may be connected to a respective one of the data lines with no intervening pass gates.

摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有可被配置用于真正双端口操作或简单双端口操作的存储器阵列。 存储器阵列包括排列成行和列的存储单元以及相关联的行地址线和数据线。 感应放大器和写入驱动器用于读取和写入数据。 预充电驱动器用于在读取操作之前预充电数据线。 阵列中的可配置多路复用器电路具有从存储器单元向读出放大器提供数据的读取路径。 多路复用器电路具有写入路径，来自写入驱动器的数据通过该路径被写入存储器单元。 读取路径和写入路径每个不包含单个传递门。 每个预充电驱动器可以连接到相应的一条数据线，而没有中间通路门。

公开(公告)号：US07499365B1

公开(公告)日：2009-03-03

申请号：US11683072

申请日：2007-03-07

申请人： Haiming Yu

发明人： Haiming Yu

IPC分类号： G11C8/00

CPC分类号： G11C11/412 ,  G11C8/16 ,  G11C11/419

摘要： A method for a read-before-write functionality for a memory within a programmable logic device (PLD) is provided. The method begins when a read operation and a write operation are initiated through two different ports of a memory simultaneously to access the same address in the memory. In order to prevent the write operation from proceeding prior to the read operation, a read-before-write control logic is provided to the control block of the port that supports the write operation. Thus, the write operation is paused until the control block of the port that supports the write operation receives a signal from a read sense amplifier indicating that the read operation is complete. The read sense amplifier is capable of detecting the completion of a read operation by monitoring the voltage difference of the read bitline. When this voltage difference reaches a threshold value, the read sense amplifier triggers a write wordline signal. The enabling of the write wordline signal causes, the data to be written to the memory.

摘要翻译： 提供了一种用于可编程逻辑器件（PLD）内的存储器的预写入功能的方法。 当通过存储器的两个不同端口同时启动读操作和写操作以访问存储器中的相同地址时，该方法开始。 为了防止写入操作在读取操作之前进行，写入前读控制逻辑被提供给支持写入操作的端口的控制块。 因此，写入操作被暂停，直到支持写入操作的端口的控制块从读取读出放大器接收到指示读取操作完成的信号。 读出读出放大器能够通过监视读取的位线的电压差来检测读取操作的完成。 当该电压差达到阈值时，读出读出放大器触发写入字线信号。 写入字线信号的使能导致数据被写入存储器。

公开(公告)号：US07130238B1

公开(公告)日：2006-10-31

申请号：US11041120

申请日：2005-01-21

申请人： Haiming Yu ,  Wei Yee Koay

发明人： Haiming Yu ,  Wei Yee Koay

IPC分类号： G11C8/05

CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C7/1075 ,  G11C8/12 ,  H03K19/1776

摘要： A random access memory circuit and a method for configuring the same. The circuit includes a first array of memory cells including a first plurality of ports and a second plurality of ports, and a second array of memory cells including a third plurality of ports and a fourth plurality of ports. Additionally, the circuit includes a plurality of switches connected to the first plurality of ports and the third plurality of ports respectively or connected to the second plurality of ports and the fourth plurality of ports respectively. Moreover, the circuit includes a plurality of sense amplifiers and a plurality of write drivers.

摘要翻译： 一种随机存取存储器电路及其配置方法。 该电路包括包括第一多个端口和第二多个端口的存储单元的第一阵列，以及包括第三多个端口和第四多个端口的第二存储单元阵列。 另外，电路包括分别连接到第一多个端口和第三多个端口的多个开关，或者分别连接到第二多个端口和第四多个端口。 此外，电路包括多个读出放大器和多个写入驱动器。

公开(公告)号：US07715271B1

公开(公告)日：2010-05-11

申请号：US12176592

申请日：2008-07-21

申请人： Haiming Yu ,  Wei Yee Koay

发明人： Haiming Yu ,  Wei Yee Koay

IPC分类号： G11C8/02

CPC分类号： H03K19/1776 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C2207/105 ,  H03K19/17744

摘要： A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory array. The dedicated read output paths bypass the width decoding logic and provide data from the memory array directly to a data bus, thereby providing improved memory performance when width decoding is not needed. The memory unit can be incorporated in programmable devices and a programmable device configuration can select either the read bypass paths or the width decoding logic. Hardware applications that require width decoding and improved memory access speed can utilize additional programmable device resources outside the memory unit to register the full width data from the memory unit and convert it to a different data width.

摘要翻译： 存储单元包括能够以不同数据宽度在存储器阵列中访问数据的宽度解码逻辑。 为了提高存储器访问速度，存储器单元还包括用于以存储器阵列的完整数据宽度访问数据的专用读取输出路径。 专用读输出路径绕过宽度解码逻辑，并将数据从存储器阵列直接提供给数据总线，从而在不需要宽度解码时提供改进的存储器性能。 存储器单元可并入可编程器件中，并且可编程器件配置可以选择读取旁路路径或宽度解码逻辑。 需要宽度解码和改善存储器访问速度的硬件应用可以利用存储器单元之外的附加可编程设备资源来从存储器单元注册全宽数据并将其转换成不同的数据宽度。

公开(公告)号：US09501407B1

公开(公告)日：2016-11-22

申请号：US13235228

申请日：2011-09-16

申请人： Ray Ruey-Hsien Hu ,  Andy L. Lee ,  David Lewis ,  Tony Ngai ,  Haiming Yu ,  Hao-Yuan Howard Chou

发明人： Ray Ruey-Hsien Hu ,  Andy L. Lee ,  David Lewis ,  Tony Ngai ,  Haiming Yu ,  Hao-Yuan Howard Chou

IPC分类号： G06F12/06 ,  G06F13/16

CPC分类号： G06F12/0607 ,  G06F13/1689 ,  Y02D10/14

摘要： A first-in-first-out memory may have first and second memory banks. A write controller may write data into the first and second memory banks. In performing write operations, the write controller may determine whether to write the data into the first bank or the second bank by evaluating a first bank empty flag and a second bank empty flag. When transitioning between writing in the first bank and the second bank, the write controller may latch a write address value indicative of the last location at which valid data was written in a given bank. A read controller may read data from the first and second memory bank. The read controller may determine when to transition between reading in the first bank and reading in the second bank by comparing a current read address to the latched write address value.

摘要翻译： 先入先出的存储器可以具有第一和第二存储体。 写控制器可以将数据写入第一和第二存储体。 在执行写入操作时，写入控制器可以通过评估第一存储体空标志和第二存储体空标志来确定是否将数据写入第一存储体或第二存储体。 当在第一组和第二组中的写入之间转换时，写入控制器可以锁存指示在给定存储体中写入有效数据的最后位置的写入地址值。 读取控制器可以从第一和第二存储体读取数据。 读取控制器可以通过将当前读取地址与锁存的写入地址值进行比较来确定何时在第一存储区中的读取和第二存储区中的读取之间转换。