公开(公告)号：US20240361906A1

公开(公告)日：2024-10-31

申请号：US18764998

申请日：2024-07-05

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Cristian P. MASGRAS

IPC: G06F3/06

CPC classification number: G06F3/0601 ,  G06F3/0604 ,  G06F3/0673

Abstract: The present disclosure is drawn to, among other things, a method of managing a magnetoresistive memory (MRAM) device. In some aspects, the method includes receiving a configuration bit from a write mode configuration register. In response to determining the configuration bit is a first value, the MRAM device is operated in a NOR emulation mode. In response to determining the configuration bit is a second value, the MRAM device is operated in a persistent memory mode.

公开(公告)号：US20220291833A1

公开(公告)日：2022-09-15

申请号：US17201924

申请日：2021-03-15

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Cristian P. MASGRAS

IPC: G06F3/06

Abstract: The present disclosure is drawn to, among other things, a method of managing a magnetoresistive memory (MRAM) device. In some aspects, the method includes receiving a configuration bit from a write mode configuration register. In response to determining the configuration bit is a first value, the MRAM device is operated in a NOR emulation mode. In response to determining the configuration bit is a second value, the MRAM device is operated in a persistent memory mode.

公开(公告)号：US20240006011A1

公开(公告)日：2024-01-04

申请号：US18467996

申请日：2023-09-15

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Jason JANESKY ,  Han Kyu LEE ,  Hamid ALMASI ,  Pedro SANCHEZ ,  Cristian P. MASGRAS ,  Iftekhar RAHMAN ,  Sumio IKEGAWA ,  Sanjeev AGGARWAL ,  Dimitri HOUSSAMEDDINE ,  Frederick Charles NEUMEYER

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C2029/0407 ,  G11C29/4401 ,  G11C29/18

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

公开(公告)号：US20230384930A1

公开(公告)日：2023-11-30

申请号：US18447031

申请日：2023-08-09

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Cristian P. MASGRAS

IPC: G06F3/06

CPC classification number: G06F3/0601 ,  G06F3/0604 ,  G06F3/0673

Abstract: The present disclosure is drawn to, among other things, a method of managing a magnetoresistive memory (MRAM) device. In some aspects, the method includes receiving a configuration bit from a write mode configuration register. In response to determining the configuration bit is a first value, the MRAM device is operated in a NOR emulation mode. In response to determining the configuration bit is a second value, the MRAM device is operated in a persistent memory mode.

公开(公告)号：US20220139488A1

公开(公告)日：2022-05-05

申请号：US17512392

申请日：2021-10-27

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Jason JANESKY ,  Han Kyu LEE ,  Hamid ALMASI ,  Pedro SANCHEZ ,  Cristian P. MASGRAS ,  Iftekhar RAHMAN ,  Sumio IKEGAWA ,  Sanjeev AGGARWAL ,  Dimitri HOUSSAMEDDINE ,  Frederick Charles NEUMEYER

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/18

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.