公开(公告)号：US20250063953A1

公开(公告)日：2025-02-20

申请号：US18933142

申请日：2024-10-31

Applicant: Everspin Technologies, Inc.

Inventor： Renu WHIG ,  Sumio IKEGAWA ,  Jon SLAUGHTER ,  Michael TRAN ,  Jacob Wang CHENCHEN ,  Ganesh Kolliyil RAJAN

IPC: H10N50/85 ,  H01F10/32 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

Abstract: A magnetoresistive device includes a magnetically fixed region and a magnetically free region positioned on opposite sides of a tunnel barrier region. One or more transition regions, including at least a first transition region and second transition region, is positioned between the magnetically fixed region and the tunnel barrier region. The first transition region includes a non-ferromagnetic transition metal and the second transition region includes an alloy including iron and boron.

公开(公告)号：US20210375342A1

公开(公告)日：2021-12-02

申请号：US17255915

申请日：2019-06-27

Applicant: Everspin Technologies, Inc.

Inventor： Jijun SUN ,  Frederick MANCOFF ,  Jason JANESKY ,  Kevin CONLEY ,  Lu HUI ,  Sumio IKEGAWA

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: Aspects of the present disclosure are directed to magnetic tunnel junction (MTJ) structures comprising multiple MTJ bits connected in series. For example, a magnetic tunnel junction (MTJ) stack according to the present disclosure may include at least a first MTJ bit and a second MTJ bit stacked above the first MTJ bit, and a resistance state of the MTJ stack may be read by passing a single read current through both the first MTJ bit and the second MTJ bit.

公开(公告)号：US20200235288A1

公开(公告)日：2020-07-23

申请号：US16744963

申请日：2020-01-16

Applicant: Everspin Technologies, Inc.

Inventor： Sumio IKEGAWA ,  Han Kyu LEE ,  Sanjeev AGGARWAL ,  Jijun SUN ,  Syed M. ALAM ,  Thomas ANDRE

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.

公开(公告)号：US20250113741A1

公开(公告)日：2025-04-03

申请号：US18897637

申请日：2024-09-26

Applicant: Everspin Technologies, Inc.

Inventor： Sumio IKEGAWA ,  Kerry Joseph NAGEL ,  Raj KUMAR ,  Syed M. ALAM

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/01

Abstract: A magnetoresistive random-access memory (MRAM) device includes a magnetoresistive tunnel junction (MTJ) device, an electrode, and a coupling layer. The MTJ device includes a free layer, a fixed layer, and a tunnel barrier layer positioned between the free layer and the fixed layer. The coupling layer is positioned between and coupling the electrode and the MTJ device. The coupling layer includes spin Hall channel (SHC) material. The free layer, the fixed layer, and the tunnel barrier layer are stacked in a first direction to form MTJ device. The electrode is nonaligned with the MTJ device such that the electrode is spaced away from the MTJ in a second direction that is different from the first direction.

公开(公告)号：US20200235289A1

公开(公告)日：2020-07-23

申请号：US16251230

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Thomas ANDRE ,  Frederick MANCOFF ,  Sumio IKEGAWA

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a plurality of magnetoresistive memory devices, wherein each magnetoresistive memory device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed in between the fixed and free magnetic regions. The magnetoresistive memory further comprises a first conductor extending adjacent each magnetoresistive memory device of the plurality of magnetoresistive devices, wherein the first conductor is in electrical contact with the free magnetic region of each magnetoresistive memory device.

公开(公告)号：US20230263071A1

公开(公告)日：2023-08-17

申请号：US17670049

申请日：2022-02-11

Applicant: Everspin Technologies, Inc.

Inventor： Sumio IKEGAWA ,  Jijun SUN ,  Monika ARORA

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetoresistive stack may include a first electrically conductive material, a fixed region having a fixed magnetic state, a free region configured to have a first magnetic state and a second magnetic state, a dielectric layer disposed between the fixed region and the free region, a spacer region, and a cap layer disposed between the spacer region and the free region. The free region may include a layer of ferromagnetic material, an insertion layer, an iPMA layer, and/or a low saturation magnetization layer.

公开(公告)号：US20240420796A1

公开(公告)日：2024-12-19

申请号：US18739969

申请日：2024-06-11

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Jacob T. WILLIAMS ,  Michael A. SADD ,  Kerry Joseph NAGEL ,  Sumio IKEGAWA ,  Frederick B. MANCOFF ,  Sanjeev AGGARWAL

IPC: G11C29/00 ,  G11C29/30 ,  G11C29/32

Abstract: A memory device including a first configuration bit group including a plurality of bits, the plurality of bits including: a plurality of configuration bits; at least one redundant configuration bit; a plurality of configuration bit multiplexers each configured to receive (i) a first input from a first bit in the plurality of bits and/or a second input from a second bit in the plurality of bits and (ii) a third input from a decoder, each of the first, second, and third inputs indicating a respective logical state, wherein the logical state includes a first state or a second state; and wherein, based on the logical state of the third input received from the decoder, each configuration bit multiplexer is configured to output: the logical state of the first input from the first bit, or the logical state of the second input from the second bit.

公开(公告)号：US20230309416A1

公开(公告)日：2023-09-28

申请号：US18123729

申请日：2023-03-20

Applicant: Everspin Technologies, Inc.

Inventor： Sumio IKEGAWA ,  Han Kyu Lee ,  Sanjeev AGGARWAL ,  Jijun SUN ,  Syed M. ALAM ,  Tom ANDRE

IPC: H10N52/80 ,  H10B61/00 ,  H10N50/85 ,  H10N52/00 ,  H10N52/01

CPC classification number: H10N52/80 ,  H10B61/22 ,  H10N50/85 ,  H10N52/00 ,  H10N52/01

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.

公开(公告)号：US20220059755A1

公开(公告)日：2022-02-24

申请号：US17521017

申请日：2021-11-08

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Sumio IKEGAWA

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32 ,  H01F41/32 ,  H01L43/08

Abstract: A magnetoresistive device comprises a fixed magnetic region positioned on or over a first electrically conductive region, an intermediate layer positioned on or over the fixed magnetic region, a free magnetic region positioned on or over the intermediate layer, and a metal insertion substance positioned in contact with the free magnetic region, wherein the metal insertion substance includes one or more transition metal elements.

公开(公告)号：US20210288245A1

公开(公告)日：2021-09-16

申请号：US17263434

申请日：2019-07-29

Applicant: Everspin Technologies, Inc.

Inventor： Renu WHIG ,  Sumio IKEGAWA ,  Jon SLAUGHTER ,  Michael TRAN ,  Jacob Wang CHENCHEN ,  Ganesh Kolliyil RAJAN

IPC: H01L43/10 ,  H01L43/12 ,  H01F10/32

Abstract: A magnetoresistive device includes a magnetically fixed region and a magnetically free region positioned on opposite sides of a tunnel barrier region. One or more transition regions, including at least a first transition region and second transition region, is positioned between the magnetically fixed region and the tunnel barrier region. The first transition region includes a non-ferromagnetic transition metal and the second transition region includes an alloy including iron and boron.