公开(公告)号：US20250113741A1

公开(公告)日：2025-04-03

申请号：US18897637

申请日：2024-09-26

Applicant: Everspin Technologies, Inc.

Inventor： Sumio IKEGAWA ,  Kerry Joseph NAGEL ,  Raj KUMAR ,  Syed M. ALAM

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/01

Abstract: A magnetoresistive random-access memory (MRAM) device includes a magnetoresistive tunnel junction (MTJ) device, an electrode, and a coupling layer. The MTJ device includes a free layer, a fixed layer, and a tunnel barrier layer positioned between the free layer and the fixed layer. The coupling layer is positioned between and coupling the electrode and the MTJ device. The coupling layer includes spin Hall channel (SHC) material. The free layer, the fixed layer, and the tunnel barrier layer are stacked in a first direction to form MTJ device. The electrode is nonaligned with the MTJ device such that the electrode is spaced away from the MTJ in a second direction that is different from the first direction.

公开(公告)号：US20250061933A1

公开(公告)日：2025-02-20

申请号：US18934463

申请日：2024-11-01

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Yaojun ZHANG ,  Frederick NEUMEYER

IPC: G11C11/16

Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.

公开(公告)号：US20220343030A1

公开(公告)日：2022-10-27

申请号：US17660253

申请日：2022-04-22

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Sanjeev AGGARWAL

IPC: G06F21/72 ,  G06F21/86 ,  H01F10/32 ,  G11C11/16

Abstract: The present disclosure is drawn to, among other things, a storage device. The storage device may include a magnetic tunnel junction (MTJ)-based storage array and a communication interface. The MTJ-based storage array may be configured to be damaged by a shorting voltage based on detection of a tamper event.

公开(公告)号：US20200235289A1

公开(公告)日：2020-07-23

申请号：US16251230

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Thomas ANDRE ,  Frederick MANCOFF ,  Sumio IKEGAWA

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a plurality of magnetoresistive memory devices, wherein each magnetoresistive memory device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed in between the fixed and free magnetic regions. The magnetoresistive memory further comprises a first conductor extending adjacent each magnetoresistive memory device of the plurality of magnetoresistive devices, wherein the first conductor is in electrical contact with the free magnetic region of each magnetoresistive memory device.

公开(公告)号：US20240361906A1

公开(公告)日：2024-10-31

申请号：US18764998

申请日：2024-07-05

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Cristian P. MASGRAS

IPC: G06F3/06

CPC classification number: G06F3/0601 ,  G06F3/0604 ,  G06F3/0673

Abstract: The present disclosure is drawn to, among other things, a method of managing a magnetoresistive memory (MRAM) device. In some aspects, the method includes receiving a configuration bit from a write mode configuration register. In response to determining the configuration bit is a first value, the MRAM device is operated in a NOR emulation mode. In response to determining the configuration bit is a second value, the MRAM device is operated in a persistent memory mode.

公开(公告)号：US20230281434A1

公开(公告)日：2023-09-07

申请号：US17893462

申请日：2022-08-23

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Dimitri HOUSSAMEDDINE ,  Sanjeev AGGARWAL

IPC: G06N3/063 ,  G11C11/54 ,  G11C11/16

CPC classification number: G06N3/063 ,  G11C11/54 ,  G11C11/161

Abstract: The present disclosure is drawn to, among other things, a device comprising input circuitry; weight operation circuitry electrically connected to the input circuitry; bias operation circuitry electrically connected to the weight operation circuitry; storage circuitry electrically connected to the weight operation circuitry and the bias operation circuitry; and activation function circuitry electrically connected to the bias operation circuitry, wherein at least the weight operation circuitry, the bias operation circuitry, and the storage circuitry are located on a same chip.

公开(公告)号：US20230245692A1

公开(公告)日：2023-08-03

申请号：US18297793

申请日：2023-04-10

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Yaojun ZHANG ,  Frederick NEUMEYER

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1657

Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.

公开(公告)号：US20190355398A1

公开(公告)日：2019-11-21

申请号：US16518146

申请日：2019-07-22

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Thomas S. ANDRE

IPC: G11C7/12 ,  G11C7/06 ,  G11C5/06

Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.

公开(公告)号：US20180122495A1

公开(公告)日：2018-05-03

申请号：US15852678

申请日：2017-12-22

Applicant: Everspin Technologies Inc.

Inventor： Thomas ANDRE ,  Jon SLAUGHTER ,  Dimitri HOUSSAMEDDINE ,  Syed M. ALAM

IPC: G11C29/50 ,  G11C11/16 ,  G06F11/08 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/50 ,  G06F11/08 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0411

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

公开(公告)号：US20170263300A1

公开(公告)日：2017-09-14

申请号：US15605508

申请日：2017-05-25

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Thomas ANDRE ,  Dimitri HOUSSAMEDDINE ,  Syed M. ALAM ,  Jon SLAUGHTER ,  Chitra SUBRAMANIAN

IPC: G11C11/16 ,  G06F12/0804

CPC classification number: G11C11/1675 ,  G06F12/0804 ,  G11C11/1677 ,  Y02D10/13

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.