公开(公告)号：US20190115060A1

公开(公告)日：2019-04-18

申请号：US16157315

申请日：2018-10-11

Applicant: Everspin Technologies, Inc.

Inventor： Sarin DESHPANDE ,  Sanjeev AGGARWAL ,  Jason JANESKY ,  Jon SLAUGHTER ,  Phillip LOPRESTI

IPC: G11C11/16 ,  H01F10/32 ,  H01L27/22 ,  H01L43/02

CPC classification number: G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01L27/228 ,  H01L43/02

Abstract: Spin-orbit-torque (SOT) control strip lines are provided along the sides of free layers in perpendicular magnetic tunnel junction devices. Current flowing through such SOT control strip lines injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used to force the magnetic state of the free layer to a particular state based on the direction of the current through the SOT control strip line. In other embodiments, the SOT provides an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction. Some embodiments have dedicated strip lines for a single magnetic tunnel junction such that a three-terminal device results. Other embodiments have multiple magnetic tunnel junctions sharing a strip line, where the strip line can be used to reset all of the magnetic tunnel junctions to the same state and can also be used as an assist such that individual magnetic tunnel junctions can be written using selection circuitry.

公开(公告)号：US20210375342A1

公开(公告)日：2021-12-02

申请号：US17255915

申请日：2019-06-27

Applicant: Everspin Technologies, Inc.

Inventor： Jijun SUN ,  Frederick MANCOFF ,  Jason JANESKY ,  Kevin CONLEY ,  Lu HUI ,  Sumio IKEGAWA

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: Aspects of the present disclosure are directed to magnetic tunnel junction (MTJ) structures comprising multiple MTJ bits connected in series. For example, a magnetic tunnel junction (MTJ) stack according to the present disclosure may include at least a first MTJ bit and a second MTJ bit stacked above the first MTJ bit, and a resistance state of the MTJ stack may be read by passing a single read current through both the first MTJ bit and the second MTJ bit.

公开(公告)号：US20150333251A1

公开(公告)日：2015-11-19

申请号：US14712130

申请日：2015-05-14

Applicant: Everspin Technologies, Inc.

Inventor： Wenchin LIN ,  Jason JANESKY

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/02 ,  G11C5/005 ,  G11C11/16 ,  H01L23/13 ,  H01L23/14 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L27/222 ,  H01L43/12 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/1441 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.

Abstract translation: 公开了用于屏蔽磁敏元件的结构和方法。 一种结构包括衬底，沉积在衬底上的底部屏蔽，具有第一表面和与第一表面相对的第二表面的磁阻半导体器件，沉积在底部屏蔽上的磁阻半导体器件的第一表面，沉积在 磁阻半导体器件的第二表面，顶部屏蔽件具有用于访问磁阻半导体器件的窗口，以及将磁阻半导体器件连接到多个导电元件的多个互连。

公开(公告)号：US20240006011A1

公开(公告)日：2024-01-04

申请号：US18467996

申请日：2023-09-15

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Jason JANESKY ,  Han Kyu LEE ,  Hamid ALMASI ,  Pedro SANCHEZ ,  Cristian P. MASGRAS ,  Iftekhar RAHMAN ,  Sumio IKEGAWA ,  Sanjeev AGGARWAL ,  Dimitri HOUSSAMEDDINE ,  Frederick Charles NEUMEYER

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C2029/0407 ,  G11C29/4401 ,  G11C29/18

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

公开(公告)号：US20220139488A1

公开(公告)日：2022-05-05

申请号：US17512392

申请日：2021-10-27

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Jason JANESKY ,  Han Kyu LEE ,  Hamid ALMASI ,  Pedro SANCHEZ ,  Cristian P. MASGRAS ,  Iftekhar RAHMAN ,  Sumio IKEGAWA ,  Sanjeev AGGARWAL ,  Dimitri HOUSSAMEDDINE ,  Frederick Charles NEUMEYER

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/18

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

公开(公告)号：US20210408371A1

公开(公告)日：2021-12-30

申请号：US17468896

申请日：2021-09-08

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kerry NAGEL ,  Jason JANESKY

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

公开(公告)号：US20190214070A1

公开(公告)日：2019-07-11

申请号：US16358414

申请日：2019-03-19

Applicant: Everspin Technologies, Inc.

Inventor： Jason JANESKY ,  Syed M. ALAM ,  Dimitri HOUSSAMEDDINE ,  Mark DEHERREA

IPC: G11C11/16 ,  G11C17/16 ,  G11C29/50 ,  G11C29/02 ,  G11C29/12

CPC classification number: G11C11/1673 ,  G11C11/16 ,  G11C11/1675 ,  G11C17/16 ,  G11C29/021 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C29/12 ,  G11C29/50

Abstract: Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.

公开(公告)号：US20180205005A1

公开(公告)日：2018-07-19

申请号：US15923842

申请日：2018-03-16

Applicant: Everspin Technologies, Inc.

Inventor： Wenchin LIN ,  Jason JANESKY

IPC: H01L43/02 ,  H01L23/552 ,  G11C5/00 ,  H01L23/14 ,  H01L27/22 ,  H01L43/12 ,  H01L23/00 ,  H01L23/498 ,  H01L23/13 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C5/005 ,  G11C11/16 ,  H01L23/13 ,  H01L23/14 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L27/222 ,  H01L43/12 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/1441 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.