公开(公告)号：US09733302B2

公开(公告)日：2017-08-15

申请号：US14846813

申请日：2015-09-06

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Zhichen Zhang ,  John M. Pigott ,  Chuanzheng Wang ,  Qilin Zhang ,  Michael J. Zunino

IPC分类号： G01R31/3187 ,  G01R31/28

CPC分类号： G01R31/2879 ,  G01R31/2817 ,  G01R31/2818

摘要： An integrated circuit (IC) having a heat-generating element, such as a power MOSFET, a current-carrying conductor coupled to the heat-generating element, a sense conductor adjacent the current-carrying conductor, and a failure-detection circuit coupled to the sense conductor. When thermal cycling of the IC causes the resistance of the sense conductor to become greater than a temperature-dependent threshold value, the failure-detection circuit generates a signal indicating that the integrated circuit will soon fail. The resistance of the sense conductor is determined by injecting a current into the sense conductor to generate a voltage. The temperature-dependent threshold value is a voltage generated by injecting a current into a reference conductor disposed away from the current-carrying and sense conductors. A voltage comparator compares the two voltages to generate the output. Alternatively, the failure-detection circuit includes a processor that calculates the temperature-dependent threshold value from a temperature measurement taken on the integrated circuit.

公开(公告)号：US09552890B2

公开(公告)日：2017-01-24

申请号：US14189529

申请日：2014-02-25

申请人： Freescale Semiconductor, Inc.

发明人： John M. Pigott ,  Randall C. Gray

IPC分类号： G11C17/06 ,  H01L23/525 ,  G11C17/16 ,  H01L27/112 ,  G11C17/18

CPC分类号： G11C17/16 ,  G11C17/06 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： The embodiments described herein provide antifuse devices and methods that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes an antifuse, a first diode coupled with the antifuse in a parallel combination, and a second diode coupled in series with the parallel combination. In such an embodiment the first diode effectively provides a bypass current path that can reduce the voltage across the antifuse when other antifuses are being programmed. As such, these embodiments can provide improved ability to tolerate programming voltages without damage or impairment of reliability.

摘要翻译： 这里描述的实施例提供可以用于各种各样的半导体器件中的反熔丝器件和方法。 在一个实施例中，提供了一种半导体器件，其包括反熔丝，与并联组合中的反熔丝耦合的第一二极管和与并联组合串联耦合的第二二极管。 在这样的实施例中，第一二极管有效地提供旁路电流路径，当其它反熔丝被编程时，可以减小反熔丝两端的电压。 因此，这些实施例可以提供改善的耐受编程电压的能力，而不会损坏或损害可靠性。

公开(公告)号：US09601479B2

公开(公告)日：2017-03-21

申请号：US14212777

申请日：2014-03-14

申请人： Freescale Semiconductor, Inc.

发明人： William E. Edwards ,  John M. Pigott

IPC分类号： H01L27/02

CPC分类号： H01L27/0255

摘要： A buffer or voltage protection circuit, a circuit including same, and an associated method of operation are disclosed. In one example embodiment, the integrated circuit includes a first input terminal, a first circuit portion having a second input terminal, and a second circuit portion. The second circuit portion includes a transistor device having first, second, and third ports, where the first and second ports are respectively electrically coupled to the first input terminal and second input terminal, respectively. Additionally, the second circuit portion also includes a diode-type device that is electrically coupled between the third port and either a power source or a power input terminal, and a buffer/driver circuit and a capacitor coupled in series between the third and second ports. The second circuit portion operates to prevent the second input terminal from being exposed to an undesirably-high voltage level.

公开(公告)号：US20160216318A1

公开(公告)日：2016-07-28

申请号：US14846813

申请日：2015-09-06

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Zhichen Zhang ,  John M. Pigott ,  Chuanzheng Wang ,  Qilin Zhang ,  Michael J. Zunino

IPC分类号： G01R31/28

CPC分类号： G01R31/2879 ,  G01R31/2817 ,  G01R31/2818

摘要： An integrated circuit (IC) having a heat-generating element, such as a power MOSFET, a current-carrying conductor coupled to the heat-generating element, a sense conductor adjacent the current-carrying conductor, and a failure-detection circuit coupled to the sense conductor. When thermal cycling of the IC causes the resistance of the sense conductor to become greater than a temperature-dependent threshold value, the failure-detection circuit generates a signal indicating that the integrated circuit will soon fail. The resistance of the sense conductor is determined by injecting a current into the sense conductor to generate a voltage. The temperature-dependent threshold value is a voltage generated by injecting a current into a reference conductor disposed away from the current-carrying and sense conductors. A voltage comparator compares the two voltages to generate the output. Alternatively, the failure-detection circuit includes a processor that calculates the temperature-dependent threshold value from a temperature measurement taken on the integrated circuit.

摘要翻译： 具有诸如功率MOSFET的发热元件，耦合到发热元件的载流导体，与载流导体相邻的感测导体的集成电路（IC）以及耦合到载流导体的故障检测电路 感应导体。 当IC的热循环使得感测导体的电阻变得大于温度相关阈值时，故障检测电路产生指示集成电路将很快失败的信号。 感测导体的电阻通过将电流注入到感测导体中以产生电压来确定。 温度相关阈值是通过将电流注入远离载流和感测导体布置的参考导体而产生的电压。 电压比较器比较两个电压以产生输出。 或者，故障检测电路包括处理器，其根据在集成电路上进行的温度测量来计算温度相关阈值。

公开(公告)号：US20150263504A1

公开(公告)日：2015-09-17

申请号：US14212777

申请日：2014-03-14

申请人： Freescale Semiconductor, Inc.

发明人： William E. Edwards ,  John M. Pigott

IPC分类号： H02H3/20

CPC分类号： H01L27/0255

摘要： A buffer or voltage protection circuit, a circuit including same, and an associated method of operation are disclosed. In one example embodiment, the integrated circuit includes a first input terminal, a first circuit portion having a second input terminal, and a second circuit portion. The second circuit portion includes a transistor device having first, second, and third ports, where the first and second ports are respectively electrically coupled to the first input terminal and second input terminal, respectively. Additionally, the second circuit portion also includes a diode-type device that is electrically coupled between the third port and either a power source or a power input terminal, and a buffer/driver circuit and a capacitor coupled in series between the third and second ports. The second circuit portion operates to prevent the second input terminal from being exposed to an undesirably-high voltage level.

摘要翻译： 公开了一种缓冲器或电压保护电路，包括其的电路以及相关联的操作方法。 在一个示例实施例中，集成电路包括第一输入端，具有第二输入端的第一电路部分和第二电路部分。 第二电路部分包括具有第一，第二和第三端口的晶体管器件，其中第一和第二端口分别电耦合到第一输入端子和第二输入端子。 此外，第二电路部分还包括电耦合在第三端口与电源或电源输入端子之间的二极管型器件，以及串联耦合在第三和第二端口之间的缓冲器/驱动器电路和电容器 。 第二电路部分操作以防止第二输入端子暴露于不期望的高电压电平。

公开(公告)号：US10139448B2

公开(公告)日：2018-11-27

申请号：US15252577

申请日：2016-08-31

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： John M. Pigott

IPC分类号： G01R31/3177 ,  G01R31/317 ,  G01R31/30 ,  G01R31/3185

摘要： An integrated circuitry includes a first logic block coupled between a first power supply terminal and a second power supply terminal. The first logic block includes a first scan chain and a configurable defect coupled to a scan output node of the first scan chain. The configurable defect has a logic node and a conductive element coupled between the logic node and the first or the second power supply terminal. The configurable defect is configured to, during a quiescent current testing mode, place a predetermined logic state on the logic node such that a current flows through the conductive element. The current can be detected by external equipment.

公开(公告)号：US09846445B2

公开(公告)日：2017-12-19

申请号：US15134512

申请日：2016-04-21

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： John M. Pigott ,  Valerian Mayega ,  Hang Fung Yip

IPC分类号： G05F1/571 ,  G05F1/575 ,  G05F1/56 ,  G05F1/569

CPC分类号： G05F1/571 ,  G05F1/562 ,  G05F1/569 ,  G05F1/575

摘要： A voltage supply regulator includes a first output resistor including a first terminal coupled to an output voltage of the voltage supply regulator and a second terminal; a first comparator including a first input coupled to a reference voltage, a second input coupled to the second terminal of the first output resistor, and an output coupled to a base of a first regulator transistor; a current mirror coupled to a collector of the first regulator transistor; and an slew rate detector coupled to the current mirror that includes a first terminal coupled to control electrodes of first and second transistors in the current mirror, and a detection bipolar junction transistor having a collector coupled to the control electrodes of the first and second transistors in the current mirror, and a base coupled to a second terminal of the capacitor.

公开(公告)号：US09385190B2

公开(公告)日：2016-07-05

申请号：US14196278

申请日：2014-03-04

申请人： Freescale Semiconductor, Inc.

发明人： John M. Pigott ,  Brent D. Rogers ,  Randall C. Gray

IPC分类号： H01L29/06 ,  H01L23/525 ,  H01L27/06 ,  H01L21/762 ,  H01L27/02

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/76283 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0676 ,  H01L2924/0002 ,  H01L2924/00

摘要： The embodiments described herein provide a semiconductor device layout and method that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes a plurality of deep trench isolation structures that define and surround a first plurality of first trench-isolated regions in the substrate, and further define a second plurality of second trench-isolated regions in the substrate. The first plurality of first trench-isolated regions is arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions. Likewise, the plurality of first columns are interleaved with the second trench-isolated regions to alternate in an array such that a second trench-isolated region is between consecutive first columns in the array and such that at least two first trench-isolated regions are between consecutive second trench-isolated regions in the array.

摘要翻译： 本文描述的实施例提供可用于各种各样的半导体器件的半导体器件布局和方法。 在一个实施例中，提供了半导体器件，其包括多个深沟槽隔离结构，其限定并围绕衬底中的第一多个第一沟槽隔离区域，并且还限定衬底中的第二多个第二沟槽隔离区域。 第一多个第一沟槽隔离区域布置在多个第一列中，其中每个第一列包括第一多个第一沟槽隔离区域中的至少两个。 类似地，多个第一列与第二沟槽隔离区交替排列成阵列中的交替，使得第二沟槽隔离区在阵列中连续的第一列之间，使得至少两个第一沟槽隔离区在 阵列中连续的第二沟槽隔离区域。

公开(公告)号：US09285244B2

公开(公告)日：2016-03-15

申请号：US14723420

申请日：2015-05-27

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： John M. Pigott ,  Fred T. Brauchler ,  William E. Edwards ,  Mike R. Garrard ,  Randall C. Gray ,  John M. Hall

IPC分类号： G01B7/14 ,  G01D5/20 ,  G01P3/488 ,  G01P3/489 ,  G01D5/244

CPC分类号： G01D5/2013 ,  G01D5/24476 ,  G01P3/488 ,  G01P3/489

摘要： An interface for processing a variable reluctance sensor signal provided by a variable reluctance sensor including an integrator, an arming comparator and a detect circuit. The integrator includes an input for receiving the variable reluctance sensor signal and an output providing an integrated signal indicative of total flux change of the variable reluctance sensor. The arming comparator compares the integrated signal with a predetermined arming threshold and provides an armed signal indicative thereof. The detect circuit provides a reset signal after the armed signal is provided to reset the integrator. A corresponding method of processing the variable reluctance sensor signal is also described.