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公开(公告)号：US09778319B2
公开(公告)日：2017-10-03
申请号：US14536017
申请日：2014-11-07
IPC分类号： G01R31/02 , G01R31/327 , G01R19/00 , H03K17/18 , H02B1/24 , G01R19/165
CPC分类号： G01R31/3274 , G01R19/16566 , G01R31/3275 , G01R31/3277
摘要： The embodiments described herein provide systems and methods for determining the health status of a sensed switch. In general, the embodiments described herein determine a measure of a health status of the sensed switch by comparing a voltage on the sensed switch, ascertaining a first comparator state under one test condition and ascertaining a second comparator state under a second test condition. The first comparator state and the second comparator state are and then compared to determine the measure of the health status of the sensed switch.
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公开(公告)号：US09601479B2
公开(公告)日：2017-03-21
申请号：US14212777
申请日：2014-03-14
发明人： William E. Edwards , John M. Pigott
IPC分类号： H01L27/02
CPC分类号： H01L27/0255
摘要： A buffer or voltage protection circuit, a circuit including same, and an associated method of operation are disclosed. In one example embodiment, the integrated circuit includes a first input terminal, a first circuit portion having a second input terminal, and a second circuit portion. The second circuit portion includes a transistor device having first, second, and third ports, where the first and second ports are respectively electrically coupled to the first input terminal and second input terminal, respectively. Additionally, the second circuit portion also includes a diode-type device that is electrically coupled between the third port and either a power source or a power input terminal, and a buffer/driver circuit and a capacitor coupled in series between the third and second ports. The second circuit portion operates to prevent the second input terminal from being exposed to an undesirably-high voltage level.
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公开(公告)号：US20150285858A1
公开(公告)日：2015-10-08
申请号：US14243386
申请日：2014-04-02
发明人： William E. Edwards , John M. Hall
IPC分类号： G01R31/28
CPC分类号： G01R31/31713 , G01R31/31701 , G06F1/00 , H04L1/00 , H04L2201/00
摘要： An integrated circuit haying normal and special operating modes includes a mode entry interlock (201) which is enabled by an initialization command and an externally supplied voltage at a first I/O terminal (204) to detect a conflict at the I/O terminal for reducing the likelihood of inadvertent entry into the special operating mode. The mode entry interlock also includes a second I/O terminal (212) for receiving a disassociated software command to enter into the special operating mode, and mode control logic (210, 216) for evaluating the received software command against any detected conflict at the I/O terminal to generate a special operating mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the first logic state.
摘要翻译： 具有正常和特殊操作模式的集成电路包括模式输入互锁（201），其通过初始化命令和外部提供的电压在第一I / O端子（204）使能以检测I / O端口上的冲突， 减少无意中进入特殊操作模式的可能性。 模式输入互锁还包括用于接收解除关联的软件命令以进入特殊操作模式的第二I / O终端（212）和模式控制逻辑（210,216），用于根据所接收的软件命令 I / O端子仅在检测到的逻辑状态与第一逻辑状态冲突时响应于接收第一和第二输入信号而产生特殊的工作模式使能信号。
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4.发明申请Protection Circuit, Circuit Employing Same, and Associated Method of Operation 有权保护电路，采用相同电路及相关操作方法公开(公告)号：US20150263504A1
公开(公告)日：2015-09-17
申请号：US14212777
申请日：2014-03-14
发明人： William E. Edwards , John M. Pigott
IPC分类号： H02H3/20
CPC分类号： H01L27/0255
摘要： A buffer or voltage protection circuit, a circuit including same, and an associated method of operation are disclosed. In one example embodiment, the integrated circuit includes a first input terminal, a first circuit portion having a second input terminal, and a second circuit portion. The second circuit portion includes a transistor device having first, second, and third ports, where the first and second ports are respectively electrically coupled to the first input terminal and second input terminal, respectively. Additionally, the second circuit portion also includes a diode-type device that is electrically coupled between the third port and either a power source or a power input terminal, and a buffer/driver circuit and a capacitor coupled in series between the third and second ports. The second circuit portion operates to prevent the second input terminal from being exposed to an undesirably-high voltage level.
摘要翻译： 公开了一种缓冲器或电压保护电路，包括其的电路以及相关联的操作方法。 在一个示例实施例中，集成电路包括第一输入端，具有第二输入端的第一电路部分和第二电路部分。 第二电路部分包括具有第一，第二和第三端口的晶体管器件，其中第一和第二端口分别电耦合到第一输入端子和第二输入端子。 此外，第二电路部分还包括电耦合在第三端口与电源或电源输入端子之间的二极管型器件，以及串联耦合在第三和第二端口之间的缓冲器/驱动器电路和电容器 。 第二电路部分操作以防止第二输入端子暴露于不期望的高电压电平。
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公开(公告)号：US10235324B2
公开(公告)日：2019-03-19
申请号：US14870770
申请日：2015-09-30
摘要： A method and apparatus provide an ability to selectively couple one of the output of the buffer or the output of the digital driver to a data terminal based upon a state of a storage location in which a stored first select indicator is stored and based upon a state of a selection signal. An external serial interface, at a semiconductor die, includes the data terminal, a selection terminal to receive the selection signal, and a clock terminal to receive a clock signal. A buffer includes an input to receive a secondary signal and an output to provide the secondary signal to the data terminal. A digital driver includes a digital output coupled to the data terminal. A first storage location has a storage state based upon the stored first select indicator. Select circuitry provides the selectively coupling.
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公开(公告)号：US09329237B2
公开(公告)日：2016-05-03
申请号：US14152262
申请日：2014-01-10
IPC分类号： H01H36/00 , H01H19/18 , G01R31/327 , H03K17/18
CPC分类号： G01R31/327 , H03K17/18
摘要： A method of switch detection is disclosed that comprises, enabling a low power mode on a switch detection device, activating a first detection circuit for detecting, at a first expiration of a first polling time interval, a first switch state of a first switch having a first priority level, the first switch state including one of a first open state and a first closed state, comparing the detected first switch state with a prior first switch state, and activating a second detection circuit for detecting, at a second expiration of a second polling time interval, a second switch state of a second switch having a second priority level, the second switch including one of a second open state and a second closed state, and the second polling time interval being greater than the first polling time interval, and the second priority level being different from the first priority level.
摘要翻译： 公开了一种开关检测方法，其特征在于包括：在开关检测装置上实现低功率模式，激活第一检测电路，用于在第一轮询时间间隔的第一次到期时检测具有第一开关的第一开关的第一开关状态， 第一优先级，第一开关状态包括第一打开状态和第一关闭状态之一，将检测到的第一开关状态与先前的第一开关状态进行比较，以及激活第二检测电路，用于在第二优先级的第二次到期时检测 轮询时间间隔，具有第二优先级的第二交换机的第二切换状态，所述第二交换机包括第二打开状态和第二关闭状态中的一个，所述第二轮询时间间隔大于所述第一轮询时间间隔，以及 第二优先级与第一优先级不同。
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公开(公告)号：US09856800B2
公开(公告)日：2018-01-02
申请号：US15038230
申请日：2013-11-22
CPC分类号： F02D37/02 , F02D41/345 , F02D41/401 , F02D2200/604 , F02P3/04 , F02P3/08
摘要： An ignition control device having an Electronic Fuel Injection mode and a Capacitive Discharge ignition mode is described. The ignition control device comprises: an output for providing an output voltage, connected or connectable to a load, the load being a fuel injection actuator of an EFI system or an ignition capacitor of a CDI system; and a driver unit connected to the output, for driving the output voltage from a low level to a high level and from the high level to the low level in dependence on an input signal, each transition of the output voltage from the low level to the high level having a low-to-high transition time which is longer for the CDI mode than for the EFI mode.
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公开(公告)号：US09506979B2
公开(公告)日：2016-11-29
申请号：US14243386
申请日：2014-04-02
发明人： William E. Edwards , John M. Hall
IPC分类号： G01R31/26 , G01R31/317 , H04L1/00 , G06F1/00
CPC分类号： G01R31/31713 , G01R31/31701 , G06F1/00 , H04L1/00 , H04L2201/00
摘要： An integrated circuit having normal and special operating modes includes a mode entry interlock (201) which is enabled by an initialization command and an externally supplied voltage at a first I/O terminal (204) to detect a conflict at the I/O terminal for reducing the likelihood of inadvertent entry into the special operating mode. The mode entry interlock also includes a second I/O terminal (212) for receiving a disassociated software command to enter into the special operating mode, and mode control logic (210, 216) for evaluating the received software command against any detected conflict at the I/O terminal to generate a special operating mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the first logic state.
摘要翻译： 具有正常和特殊操作模式的集成电路包括：模式输入互锁（201），其通过初始化命令和第一I / O端子（204）处的外部提供的电压使能，以检测I / O端口处的冲突 减少无意中进入特殊操作模式的可能性。 模式输入互锁还包括用于接收解除关联的软件命令以进入特殊操作模式的第二I / O终端（212）和模式控制逻辑（210,216），用于根据所接收的软件命令 I / O端子仅在检测到的逻辑状态与第一逻辑状态冲突时响应于接收第一和第二输入信号而产生特殊的工作模式使能信号。
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公开(公告)号：US09366548B2
公开(公告)日：2016-06-14
申请号：US14045473
申请日：2013-10-03
摘要： The embodiments described herein include systems with a variable reluctance sensor (VRS) interface and methods of their operation that may reduce the probability of erroneous transitions in a resulting generated detect signal. As such, the VRS interface can improve the accuracy of position and/or motion determinations, and thus can improve the performance of a wide variety of devices that use variable reluctance sensors. In one embodiment the VRS interface uses a comparator with hysteresis to generate a trailing edge signal. In another embodiment the VRS interface uses bias voltages to reduce the probability of erroneous transitions in a trailing edge signal. In either case the VRS interface can prevent erroneous transitions in the detect signal and thus may improve the performance and accuracy of the system.
摘要翻译： 这里描述的实施例包括具有可变磁阻传感器（VRS）接口的系统及其操作的方法，其可以降低产生的所产生的检测信号中的错误转换的可能性。 因此，VRS接口可以提高位置和/或运动确定的精度，从而可以提高使用可变磁阻传感器的各种各样的设备的性能。 在一个实施例中，VRS接口使用具有滞后的比较器来产生后沿信号。 在另一个实施例中，VRS接口使用偏置电压来降低后沿信号中错误转换的概率。 在任一种情况下，VRS接口可以防止检测信号中的错误转换，从而可以提高系统的性能和精度。
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公开(公告)号：US09285244B2
公开(公告)日：2016-03-15
申请号：US14723420
申请日：2015-05-27
发明人： John M. Pigott , Fred T. Brauchler , William E. Edwards , Mike R. Garrard , Randall C. Gray , John M. Hall
CPC分类号： G01D5/2013 , G01D5/24476 , G01P3/488 , G01P3/489
摘要： An interface for processing a variable reluctance sensor signal provided by a variable reluctance sensor including an integrator, an arming comparator and a detect circuit. The integrator includes an input for receiving the variable reluctance sensor signal and an output providing an integrated signal indicative of total flux change of the variable reluctance sensor. The arming comparator compares the integrated signal with a predetermined arming threshold and provides an armed signal indicative thereof. The detect circuit provides a reset signal after the armed signal is provided to reset the integrator. A corresponding method of processing the variable reluctance sensor signal is also described.
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