公开(公告)号：US11929400B2

公开(公告)日：2024-03-12

申请号：US17360980

申请日：2021-06-28

申请人： FUJI ELECTRIC CO., LTD.

发明人： Naoyuki Ohse ,  Takahito Kojima

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L29/16 ,  H01L29/872

CPC分类号： H01L29/1608 ,  H01L21/28 ,  H01L29/66143 ,  H01L29/872

摘要： A method of manufacturing a silicon carbide semiconductor device, including forming a first-conductivity-type region in a SiC semiconductor substrate, selectively forming a plurality of second-conductivity-type regions in the first-conductivity-type region, forming an interlayer insulating film covering the first-conductivity-type region and the second-conductivity-type regions, selectively removing the interlayer insulating film to form a plurality of openings exposing the second-conductivity-type regions, forming, in each opening, a layered metal film having a cap film stacked on an aluminum film, thermally diffusing aluminum atoms in the aluminum film to thereby form a plurality of second-conductivity-type high-concentration regions, removing the layered metal film, selectively removing the interlayer insulating film to form a contact hole, forming a first electrode by sequentially stacking a titanium film and a metal film containing aluminum on the first surface of the semiconductor substrate in the contact hole, and forming a second electrode on the second main surface of the semiconductor substrate.

公开(公告)号：US10374080B2

公开(公告)日：2019-08-06

申请号：US15943696

申请日：2018-04-02

申请人： FUJI ELECTRIC CO., LTD.

发明人： Naoyuki Ohse ,  Yusuke Kobayashi ,  Takahito Kojima ,  Shinsuke Harada

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/47 ,  H01L29/16 ,  H01L29/872 ,  H01L29/06

摘要： On a front surface of a semiconductor base, an n−-type drift layer, a p-type base layer, an n++-type source region, and a gate trench and a contact trench penetrating the n++-type source region and the p-type base layer and reaching the n−-type drift layer are provided. The contact trench is provided separated from the gate trench. A Schottky metal is embedded in the contact trench and forms a Schottky contact with the n−-type drift layer at a side wall of the contact trench. An ohmic metal is provided at a bottom of the contact trench and forms an ohmic contact with the n−-type drift layer.

公开(公告)号：US10008592B1

公开(公告)日：2018-06-26

申请号：US15800884

申请日：2017-11-01

申请人： FUJI ELECTRIC CO., LTD. ,  NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

发明人： Takahito Kojima ,  Yasunori Tanaka ,  Shinsuke Harada

IPC分类号： H01L31/0312 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/417 ,  H01L29/739 ,  H01L29/08

摘要： Each first p+-type region is provided between adjacent trenches embedded with a MOS gate and is in contact with a p-type base region. Second p+-type regions face a bottom and bottom corner portions of the trenches in a depth direction. An n-type CS region is a current spread layer provided between the first p+-type regions and the second p+-type regions. The n-type CS region is provided only in an active region and an end thereof is positioned at a boundary of the active region and an edge termination region. Further, the n-type CS region extends to be flush with or farther inward than an outermost first p+-type region. An outermost p++-type contact region extends from a drop between the active region and the edge termination region to the edge termination region and extends beyond the n-type CS region.

公开(公告)号：US20190245079A1

公开(公告)日：2019-08-08

申请号：US16234939

申请日：2018-12-28

申请人： FUJI ELECTRIC CO., LTD.

发明人： Fumikazu Imai ,  Takahito Kojima

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/36

CPC分类号： H01L29/7813 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/66734

摘要： A vertical MOSFET having a trench gate structure includes an n−-type drift layer and a p-type base layer formed by epitaxial growth. In the p-type base layer, an n+-type source region is provided. A trench that penetrates the p-type base layer and the n+-type source region, and reaches the n−-type drift layer is provided. The first p+-type region is in contact with a bottom of the trench and is implanted with an impurity that determines a conductivity type of the first p+-type region and a first element that bonds with a second element that is displaced by the impurity, the impurity and the second element being implanted at a predetermined ratio.

公开(公告)号：US20180350975A1

公开(公告)日：2018-12-06

申请号：US15961013

申请日：2018-04-24

申请人： FUJI ELECTRIC CO., LTD.

发明人： Takahito Kojima ,  Shinsuke Harada ,  Yasuhiko Oonishi

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/10

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42376 ,  H01L29/66068

摘要： On a surface of an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate, first and second p+-type base regions are formed in the n-type silicon carbide epitaxial layer, an n-type region is formed in the n-type silicon carbide epitaxial layer, a p-type base layer is formed on the n-type region, an n+-type source region and a p++-type contact region are formed in the p-type base layer, and a trench is formed to a position shallower than the second p+-type base region and penetrates the p-type base layer. A first sidewall angle of the trench at a position of the p-type base layer is 80° to 90° with respect to a main surface. A difference of the first sidewall angle and a second sidewall angle of the trench at a position deeper than a boundary of the p-type base layer and the n-type region is 1° to 25°.

公开(公告)号：US20180358430A1

公开(公告)日：2018-12-13

申请号：US15993336

申请日：2018-05-30

申请人： FUJI ELECTRIC CO., LTD.

发明人： Yusuke KOBAYASHI ,  Naoyuki Ohse ,  Shinsuke Harada ,  Takahito Kojima

IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/04

摘要： A vertical MOSFET having a trench gate structure includes an n−-type drift layer and a p-type base layer formed by epitaxial growth. In the n−-type drift layer, an n-type region, an upper second p+-type region, a lower second p+-type region and a first p+-type region are provided. The lower second p+-type region is provided orthogonal to a trench, and a total mathematical area regions that are between the first p+-type region and the p-type base layer and that include the n-type region is at least two times a total mathematical area of regions that are between the first p+-type region and the p-type base layer and that include the upper second p+-type region.

公开(公告)号：US20180175147A1

公开(公告)日：2018-06-21

申请号：US15846075

申请日：2017-12-18

申请人： FUJI ELECTRIC CO., LTD. ,  NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

发明人： Naoyuki OHSE ,  Yusuke Kobayashi ,  Takahito Kojima ,  Shinsuke Harada

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L29/1041 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7813

摘要： A vertical MOSFET of a trench gate structure includes an n−-type drift layer and a p+-type base layer formed by epitaxial growth. The vertical MOSFET includes a trench that penetrates the n−-type drift layer and the p+-type base layer. A low-concentration thin film is provided in the trench. The low-concentration thin film is in contact with the p+-type base layer and is of the same conductivity type as the p+-type base layer. Further, the low-concentration thin film has an impurity concentration that is lower than that of the p+-type base layer.

公开(公告)号：US09978842B2

公开(公告)日：2018-05-22

申请号：US15071398

申请日：2016-03-16

申请人： Kabushiki Kaisha Toshiba ,  National Institute of Advanced Industrial Science and Technology ,  Fuji Electric Co., Ltd.

发明人： Keiko Ariyoshi ,  Tatsuo Shimizu ,  Takashi Shinohe ,  Junji Senzaki ,  Shinsuke Harada ,  Takahito Kojima

IPC分类号： H01L29/16 ,  H01L29/04 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/04

CPC分类号： H01L29/1608 ,  H01L21/0214 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/02529 ,  H01L21/049 ,  H01L29/045 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813

摘要： According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first electrode, a second electrode, a control electrode and an insulating film. The first semiconductor region is of a first conductivity type and includes SiC. The second semiconductor region is provided on the first semiconductor region and has a first surface. The second semiconductor region is of a second conductivity type and includes SiC. The third semiconductor region is provided on the second semiconductor region, is of the first conductivity type and includes SiC. The first and second electrodes are electrically connected to the third semiconductor region. The control electrode is provided on the second semiconductor region. The insulating film is provided between the second semiconductor region and the control electrode. The insulating film contacts the first surface and the control electrode and includes nitrogen.

公开(公告)号：US11411093B2

公开(公告)日：2022-08-09

申请号：US17106974

申请日：2020-11-30

申请人： FUJI ELECTRIC CO., LTD.

发明人： Takahito Kojima ,  Naoyuki Ohse

IPC分类号： H01L21/04 ,  H01L29/45 ,  H01L29/66 ,  H01L29/16 ,  H01L29/872 ,  H01L29/47

摘要： In a method of manufacturing a silicon carbide semiconductor device that is a silicon carbide diode having a JBS structure including a mixture of a Schottky junction and a pn junction and that maintains low forward voltage through a SBD structure and enhances surge current capability, nickel silicide films are formed in an oxide film by self-alignment by causing a semiconductor substrate and a metal material film to react with one another through two sessions of heat treatment including a low-temperature heat treatment and a high-temperature heat treatment, the metal material film including sequentially a first nickel film, an aluminum film, and a second nickel film, the first nickel film being in contact with an entire area of a connecting region of a FLR and p-type regions respectively exposed in openings of the oxide film.

公开(公告)号：US11309438B2

公开(公告)日：2022-04-19

申请号：US17108591

申请日：2020-12-01

申请人： FUJI ELECTRIC CO., LTD.

发明人： Naoyuki Ohse ,  Takahito Kojima ,  Yuichi Hashizume ,  Takafumi Uchida

IPC分类号： H01L29/872 ,  H01L21/04 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L29/47

摘要： A semiconductor device having, in a plan view, a termination region surrounding an active region. The semiconductor device includes a semiconductor substrate containing silicon carbide, a first-conductivity-type region provided in the semiconductor substrate at its first main surface, a plurality of first second-conductivity-type regions selectively formed in the semiconductor substrate at its first main surface, a plurality of silicide films respectively in ohmic contact with the first second-conductivity-type regions, a first electrode that is in contact with the silicide films to form ohmic regions, with the first second-conductivity-type regions to form non-operating regions, and with the first-conductivity-type region to form Schottky regions, a second electrode provided at a second main surface of the semiconductor substrate, and a second second-conductivity-type region provided in the termination region. The ohmic regions, the non-operating regions and the Schottky regions are formed in the active region in a striped pattern. The second second-conductivity-type region connects the ohmic regions and the non-operating regions.