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    PROCESS FOR MANUFACTURING AN ARRAY OF CELLS INCLUDING SELECTION BIPOLAR JUNCTION TRANSISTORS WITH PROJECTING CONDUCTION REGIONS
    6.
    发明申请
    PROCESS FOR MANUFACTURING AN ARRAY OF CELLS INCLUDING SELECTION BIPOLAR JUNCTION TRANSISTORS WITH PROJECTING CONDUCTION REGIONS 审中-公开
    用于制造具有投影导电区域的选择性双极晶体管的电池阵列的方法

    公开(公告)号：US20090014709A1

    公开(公告)日：2009-01-15

    申请号：US12169452

    申请日：2008-07-08

    申请人： Fabio Pellizzer ,  Augusto Benvenuti ,  Paolo Cappelletti ,  Roberto Bez ,  Agostino Pirovano

    发明人： Fabio Pellizzer ,  Augusto Benvenuti ,  Paolo Cappelletti ,  Roberto Bez ,  Agostino Pirovano

    IPC分类号： H01L29/06 ,  H01L21/82

    CPC分类号： H01L27/1022 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

    摘要： A process manufactures an array of cells in a body of semiconductor material wherein a common conduction region of a first conductivity type and a plurality of shared control regions, of a second conductivity type, are formed in the body. The shared control regions extend on the common conduction region and are laterally delimited by insulating regions. Then, a grid-like layer is formed on the body to delimit a first plurality of empty regions directly overlying the body and conductive regions of semiconductor material and the first conductivity type are formed by filling the first plurality of empty regions, each conductive region forming, together with the common conduction region and an own shared control region, a bipolar junction transistor.

    摘要翻译： 一种方法制造半导体材料体中的单元阵列，其中在体内形成有第二导电类型的共同导电区域和多个第二导电类型的共用控制区域。 共享控制区域在公共导电区域上延伸并由绝缘区域侧向限定。 然后，在主体上形成网状层，以界定直接覆盖在主体和半导体材料的导电区域上的第一多个空区域，并且通过填充第一多个空区域形成第一导电类型，每个导电区域形成 与公共导电区域和自己的共用控制区域一起，双极结型晶体管。

    Phase change memory with ovonic threshold switch
    7.
    发明授权
    Phase change memory with ovonic threshold switch 有权
    相位变化记忆体带有超声门限开关

    公开(公告)号：US08084789B2

    公开(公告)日：2011-12-27

    申请号：US12700440

    申请日：2010-02-04

    申请人： Fabio Pellizzer ,  Agostino Pirovano

    发明人： Fabio Pellizzer ,  Agostino Pirovano

    IPC分类号： H01L29/76

    CPC分类号： H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1675

    摘要： A phase change memory includes a memory element and a selection element. The memory element is embedded in a dielectric and includes a resistive element having at least one sublithographic dimension and a storage region in contact with the resistive element. The selection element includes a chalcogenic material embedded in a dielectric. The chalcogenic material and the storage region are part of a stack having a common etched edge.

    摘要翻译： 相变存储器包括存储元件和选择元件。 存储元件嵌入在电介质中，并且包括具有至少一个亚光刻尺寸的电阻元件和与电阻元件接触的存储区域。 选择元件包括埋在电介质中的硫属材料。 硫属材料和存储区域是具有共同蚀刻边缘的堆叠的一部分。

    Memory including bipolar junction transistor select devices
    8.
    发明授权
    Memory including bipolar junction transistor select devices 有权
    存储器包括双极结型晶体管选择器件

    公开(公告)号：US07898848B2

    公开(公告)日：2011-03-01

    申请号：US11788909

    申请日：2007-04-23

    申请人： Agostino Pirovano ,  Fabio Pellizzer

    发明人： Agostino Pirovano ,  Fabio Pellizzer

    IPC分类号： G11C11/00

    CPC分类号： H01L29/735 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/0207 ,  H01L27/1022 ,  H01L27/24

    摘要： An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions overlying the common region. Each shared control region forms the control regions of a plurality of adjacent selection transistors and accommodates the first regions of the plurality of adjacent selection transistors as well as contact portions of the shared control region. Blocks of adjacent selection transistors of the plurality of selection transistors share a contact portion and the first regions of a block of adjacent selection transistors are arranged along the shared control region between two contact portions. A plurality of biasing structures are formed between pairs of first regions of adjacent selection transistors, for modifying a charge distribution in the shared control region below the biasing structures.

    摘要翻译： 阵列由多个单元形成，其中每个单元由具有第一，第二和控制区域的双极结选择晶体管形成。 单元包括形成选择晶体管的第二区域的公共区域和覆盖在公共区域上的多个共享控制区域。 每个共享控制区域形成多个相邻选择晶体管的控制区域并且容纳多个相邻选择晶体管的第一区域以及共享控制区域的接触部分。 多个选择晶体管的相邻选择晶体管的块共享接触部分，并且沿着两个接触部分之间的共享控制区域布置相邻选择晶体管的块的第一区域。 在相邻选择晶体管的第一区域对之间形成多个偏置结构，用于修改偏置结构下方的共享控制区域中的电荷分布。

    Multilevel programming of phase change memory cells
    9.
    发明授权
    Multilevel programming of phase change memory cells 有权
    相变存储器单元的多级编程

    公开(公告)号：US07515460B2

    公开(公告)日：2009-04-07

    申请号：US11606762

    申请日：2006-11-30

    申请人： George Gordon ,  Stephen Hudgens ,  Fabio Pellizzer ,  Agostino Pirovano

    发明人： George Gordon ,  Stephen Hudgens ,  Fabio Pellizzer ,  Agostino Pirovano

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/79

    摘要： A method for programming a phase change memory cell is discussed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states, in which the phase change material includes both crystalline regions and amorphous regions and has intermediate resistance levels. According to the method, a plurality of programming pulses are provided to the phase change memory cell; programming energies respectively associated to the programming pulses are lower than a threshold energy which is required to bring the phase change material to the second state.

    摘要翻译： 讨论了一种编程相变存储单元的方法。 相变存储单元包括具有第一状态的相变材料的存储元件，其中所述相变材料是晶体并且具有最小电阻水平，所述相变材料是非晶态且具有最大电阻的第二状态 电平和多个中间状态，其中相变材料包括结晶区域和非晶区域并具有中等电阻水平。 根据该方法，向相变存储单元提供多个编程脉冲; 分别与编程脉冲相关联的编程能量低于使相变材料进入第二状态所需的阈值能量。

    Memory including bipolar junction transistor select devices
    10.
    发明申请
    Memory including bipolar junction transistor select devices 有权
    存储器包括双极结型晶体管选择器件

    公开(公告)号：US20080259677A1

    公开(公告)日：2008-10-23

    申请号：US11788909

    申请日：2007-04-23

    申请人： Agostino Pirovano ,  Fabio Pellizzer

    发明人： Agostino Pirovano ,  Fabio Pellizzer

    IPC分类号： G11C11/00 ,  H01L21/331

    CPC分类号： H01L29/735 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/0207 ,  H01L27/1022 ,  H01L27/24

    摘要： An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions overlying the common region. Each shared control region forms the control regions of a plurality of adjacent selection transistors and accommodates the first regions of the plurality of adjacent selection transistors as well as contact portions of the shared control region. Blocks of adjacent selection transistors of the plurality of selection transistors share a contact portion and the first regions of a block of adjacent selection transistors are arranged along the shared control region between two contact portions. A plurality of biasing structures are formed between pairs of first regions of adjacent selection transistors, for modifying a charge distribution in the shared control region below the biasing structures.

    摘要翻译： 阵列由多个单元形成，其中每个单元由具有第一，第二和控制区域的双极结选择晶体管形成。 单元包括形成选择晶体管的第二区域的公共区域和覆盖在公共区域上的多个共享控制区域。 每个共享控制区域形成多个相邻选择晶体管的控制区域并且容纳多个相邻选择晶体管的第一区域以及共享控制区域的接触部分。 多个选择晶体管的相邻选择晶体管的块共享接触部分，并且沿着两个接触部分之间的共享控制区域布置相邻选择晶体管的块的第一区域。 在相邻选择晶体管的第一区域对之间形成多个偏置结构，用于修改偏置结构下方的共享控制区域中的电荷分布。