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    PROCESS FOR MANUFACTURING AN ARRAY OF CELLS INCLUDING SELECTION BIPOLAR JUNCTION TRANSISTORS WITH PROJECTING CONDUCTION REGIONS
    4.
    发明申请
    PROCESS FOR MANUFACTURING AN ARRAY OF CELLS INCLUDING SELECTION BIPOLAR JUNCTION TRANSISTORS WITH PROJECTING CONDUCTION REGIONS 审中-公开
    用于制造具有投影导电区域的选择性双极晶体管的电池阵列的方法

    公开(公告)号：US20090014709A1

    公开(公告)日：2009-01-15

    申请号：US12169452

    申请日：2008-07-08

    申请人： Fabio Pellizzer ,  Augusto Benvenuti ,  Paolo Cappelletti ,  Roberto Bez ,  Agostino Pirovano

    发明人： Fabio Pellizzer ,  Augusto Benvenuti ,  Paolo Cappelletti ,  Roberto Bez ,  Agostino Pirovano

    IPC分类号： H01L29/06 ,  H01L21/82

    CPC分类号： H01L27/1022 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

    摘要： A process manufactures an array of cells in a body of semiconductor material wherein a common conduction region of a first conductivity type and a plurality of shared control regions, of a second conductivity type, are formed in the body. The shared control regions extend on the common conduction region and are laterally delimited by insulating regions. Then, a grid-like layer is formed on the body to delimit a first plurality of empty regions directly overlying the body and conductive regions of semiconductor material and the first conductivity type are formed by filling the first plurality of empty regions, each conductive region forming, together with the common conduction region and an own shared control region, a bipolar junction transistor.

    摘要翻译： 一种方法制造半导体材料体中的单元阵列，其中在体内形成有第二导电类型的共同导电区域和多个第二导电类型的共用控制区域。 共享控制区域在公共导电区域上延伸并由绝缘区域侧向限定。 然后，在主体上形成网状层，以界定直接覆盖在主体和半导体材料的导电区域上的第一多个空区域，并且通过填充第一多个空区域形成第一导电类型，每个导电区域形成 与公共导电区域和自己的共用控制区域一起，双极结型晶体管。

    Self-Aligned Bipolar Junction Transistors
    7.
    发明申请
    Self-Aligned Bipolar Junction Transistors 审中-公开
    自对准双极结晶体管

    公开(公告)号：US20110084247A1

    公开(公告)日：2011-04-14

    申请号：US12969652

    申请日：2010-12-16

    申请人： Fabio Pellizzer ,  Roberto Bez ,  Paola Zuliani ,  Augusto Benvenuti

    发明人： Fabio Pellizzer ,  Roberto Bez ,  Paola Zuliani ,  Augusto Benvenuti

    IPC分类号： H01L45/00 ,  H01L27/082

    CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L27/1022 ,  H01L27/24 ,  H01L29/66272

    摘要： A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.

    摘要翻译： 通过形成公共导电区域，在公共导电区域上的自身有效区域中延伸的多个控制区域，多个硅化物保护带和至少一个控制接触区域来形成多个双极晶体管。 在第二导电区域和控制接触区域上形成硅化物区域。 可以通过在所选择的硅化物保护条的第一侧选择性地注入第一导电类型的掺杂剂区域来形成第二导电区域。 通过在所选择的硅化物保护带的第二侧选择性地注入相反的导电型掺杂剂来形成控制接触区域。

    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured
    8.
    发明授权
    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured 有权
    因此制造Cu-damascene技术和相变存储器阵列中的相变存储器阵列的制造方法

    公开(公告)号：US07606056B2

    公开(公告)日：2009-10-20

    申请号：US11317622

    申请日：2005-12-22

    申请人： Fabio Pellizzer ,  Roberto Bez ,  Maria Santina Marangon ,  Roberta Piva ,  Laura Aina

    发明人： Fabio Pellizzer ,  Roberto Bez ,  Maria Santina Marangon ,  Roberta Piva ,  Laura Aina

    IPC分类号： G11C5/06

    CPC分类号： H01L45/1691 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    摘要： A process for manufacturing a phase change memory array includes the steps of: forming a plurality of phase change memory cells in an array region of a semiconductor wafer, the phase change memory cells arranged in rows and columns according to a row direction and to a column direction, respectively; forming a control circuit in a control region of the semiconductor wafer; forming a plurality of first bit line portions for mutually connecting phase change memory cells arranged on a same column; forming first level electrical interconnection structures; and forming second level electrical interconnection structures above the first level electrical interconnection structures. The first level electrical interconnection structures include second bit line portions laying on and in contact with the first bit line portions and projecting from the first bit line portions in the column direction for connecting the first bit line portions to the control circuit.

    摘要翻译： 一种相变存储器阵列的制造方法包括以下步骤：在半导体晶片的阵列区域中形成多个相变存储单元，根据行方向排列成行和列的相变存储单元和列 方向; 在所述半导体晶片的控制区域中形成控制电路; 形成多个第一位线部分，用于相互连接布置在同一列上的相变存储器单元; 形成一级电互连结构; 以及在所述第一级电互连结构之上形成第二级电互连结构。 第一级电互连结构包括布置在第一位线部分上并与第一位线部分接触的第二位线部分，并且在列方向上从第一位线部分突出以将第一位线部分连接到控制电路。

    Content addressable memory cell
    9.
    发明授权
    Content addressable memory cell 有权
    内容可寻址存储单元

    公开(公告)号：US07227765B2

    公开(公告)日：2007-06-05

    申请号：US10970842

    申请日：2004-10-20

    申请人： Guido De Sandre ,  Roberto Bez ,  Fabio Pellizzer

    发明人： Guido De Sandre ,  Roberto Bez ,  Fabio Pellizzer

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    摘要： A content addressable memory cell for a non-volatile content addressable memory, including a non-volatile storage element for storing a content digit, a selection input for selecting the memory cell, a search input for receiving a search digit, and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage element include at least one phase-change memory element for storing in a non-volatile way the respective content digit.

    摘要翻译： 一种用于非易失性内容可寻址存储器的内容可寻址存储器单元，包括用于存储内容数位的非易失性存储元件，用于选择存储单元的选择输入，用于接收搜索数字的搜索输入以及比较电路装置 用于将搜索数字与内容数字进行比较，并用于驱动存储器单元的匹配输出，以便发出内容数字和搜索数字之间的匹配。 非易失性存储元件包括用于以非易失性方式存储相应内容数字的至少一个相变存储器元件。

    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby
    10.
    发明申请
    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby 有权
    用于制造Cu-镶嵌技术中的相变存储器阵列的方法和由其制造的相变存储器阵列

    公开(公告)号：US20050064606A1

    公开(公告)日：2005-03-24

    申请号：US10902508

    申请日：2004-07-29

    申请人： Fabio Pellizzer ,  Roberto Bez

    发明人： Fabio Pellizzer ,  Roberto Bez

    IPC分类号： H01L27/24 ,  H01L21/00

    CPC分类号： H01L27/2472 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    摘要： A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells, arranged in rows and columns; and forming a plurality of resistive bit lines for connecting PCM cells arranged on a same column, each resistive bit lines comprising a respective phase change material portion, covered by a respective barrier portion. After forming the resistive bit lines, electrical connection structures for the resistive bit lines are formed directly in contact with the barrier portions of the resistive bit lines.

    摘要翻译： 一种制造相变存储器阵列的方法，包括以下步骤：形成以行和列排列的多个PCM单元; 以及形成用于连接布置在同一列上的PCM单元的多个电阻位线，每个电阻位线包括由相应的阻挡部分覆盖的各个相变材料部分。 在形成电阻位线之后，电阻位线的电连接结构直接形成为与电阻位线的势垒部分接触。