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1.发明授权公开(公告)号：US07560782B2
公开(公告)日：2009-07-14
申请号：US11605190
申请日：2006-11-27
IPC分类号： H01L29/76
CPC分类号： H01L27/24 , G11C13/0004 , G11C13/003 , G11C2213/74 , G11C2213/76 , G11C2213/79 , H01L21/8249 , H01L27/0705
摘要： An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type and a MOSFET of planar type, contiguous to one another. The active area accommodates a collector region; a bipolar base region contiguous to the collector region; an emitter region within the bipolar base region; a source region, arranged at a distance from the bipolar base region; a drain region; a channel region arranged between the source region and the drain region; and a well region. The drain region and the bipolar base region are contiguous and form a common base structure shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device has a high input impedance and is capable of driving high currents, while only requiring a small integration area.
摘要翻译： 集成晶体管器件形成在半导体材料的芯片中，其具有限定容纳垂直型双极晶体管的有源区域的电绝缘区域和彼此相邻的平面型MOSFET。 活动区域容纳收集区域; 与集电极区域相邻的双极基极区域; 在双极基区内的发射极区; 源极区域，布置在距离双极基极区域一定距离处; 漏区; 布置在源极区域和漏极区域之间的沟道区域; 和一个井区。 漏极区域和双极基极区域是连续的，并且形成由双极晶体管和MOSFET共享的公共基极结构。 因此，集成晶体管器件具有高输入阻抗并且能够驱动高电流，同时仅需要小的积分面积。
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2.发明授权公开(公告)号：US06410387B1
公开(公告)日：2002-06-25
申请号：US09449044
申请日：1999-11-24
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546 , Y10S438/981
摘要： A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, forming from a second polysilicon layer control gate electrodes for the memory cells, and gate electrodes for the second transistors; in the first portions of the semiconductor substrate, forming source and drain regions for the first transistors; in the second portions of the semiconductor substrate, forming source and drain regions for the memory cells; in the third portions of the semiconductor substrate, forming source and drain regions for the second transistors.
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3.发明授权Method for evaluating the dielectric layer of nonvolatile EPROM, EEPROM and flash-EEPROM memories 失效用于评估非易失性EPROM，EEPROM和闪存EEPROM存储器介质层的方法
公开(公告)号：US5712816A
公开(公告)日：1998-01-27
申请号：US685782
申请日：1996-07-24
IPC分类号： G11C17/00 , G11C29/00 , G11C29/50 , G11C29/56 , H01L21/66 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： G11C29/50004 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/5004 , G11C2029/5006
摘要： A method employing a test structure identical to the memory array whose gate oxide or interpoly dielectric quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is subjected to electrical stress of such a value and polarity as to extract electrons from the floating gate of the defective-gate-oxide or defective-interpoly-dielectric cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A subthreshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide or interpoly dielectric of EPROM, EEPROM and flash-EEPROM memories.
摘要翻译： 除了电池彼此电连接的事实之外，采用与要求栅极氧化物或多晶硅电介质质量的存储器阵列相同的测试结构的方法。 该测试结构受到这样一个值和极性的电应力，以从缺陷栅极氧化物或缺陷 - 互聚电解质的浮栅中提取电子，并且因此改变电池的特性，同时留下电荷 无缺陷细胞不变。 以这种方式，只有有缺陷的单元的阈值被改变。 然后将亚阈值电压施加到测试结构，并且测量与结构中存在至少一个有缺陷单元有关的通过单元的漏极电流。 电流 - 电压特性的测量和分析提供了确定缺陷单元的数量。 该方法适用于EPROM，EEPROM和闪存EEPROM存储器的栅极氧化物或多晶硅电介质的在线质量控制。
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公开(公告)号：US07001800B2
公开(公告)日：2006-02-21
申请号：US10911220
申请日：2004-08-03
IPC分类号： H01L21/82
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531 , H01L27/11546
摘要： A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.
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5.发明授权Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry 有权在同一芯片中集成非易失性存储器和高性能逻辑电路的过程公开(公告)号：US06713347B2
公开(公告)日：2004-03-30
申请号：US10158424
申请日：2002-05-29
IPC分类号： H01L29792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546 , Y10S438/981
摘要： A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, forming from a second polysilicon layer control gate electrodes for the memory cells, and gate electrodes for the second transistors; in the first portions of the semiconductor substrate, forming source and drain regions for the first transistors; in the second portions of the semiconductor substrate, forming source and drain regions for the memory cells; in the third portions of the semiconductor substrate, forming source and drain regions for the second transistors.
摘要翻译： 一种用于制造集成电路的方法，该集成电路包括低工作电压，高性能逻辑电路和具有高于逻辑电路的低工作电压的高工作电压的嵌入式存储器件，其提供：在半导体的第一部分上 衬底，形成用于在高工作电压下工作的第一晶体管的第一栅氧化层; 在所述半导体衬底的第二部分上形成用于所述存储器件的存储器单元的第二栅氧化层; 在第一和第二栅氧化层上形成第一晶体管的第一多晶硅层栅电极和用于存储单元的浮栅电极; 在存储单元的浮栅电极上形成介电层; 在半导体衬底的第三部分上形成用于在低工作电压下工作的第二晶体管的第三栅极氧化层; 在所述电介质层和所述半导体衬底的所述第三部分上，从第二多晶硅层形成用于所述存储单元的控制栅电极和用于所述第二晶体管的栅电极; 在半导体衬底的第一部分中，形成用于第一晶体管的源区和漏区; 在半导体衬底的第二部分中，形成用于存储单元的源区和漏区; 在半导体衬底的第三部分中，形成用于第二晶体管的源区和漏极区。
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公开(公告)号：US5913120A
公开(公告)日：1999-06-15
申请号：US502329
申请日：1995-07-13
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/11521 , H01L27/11541 , H01L27/11546 , Y10S438/979
摘要： A process for simultaneously fabricating memory cells, transistors, and diodes for protecting the tunnel oxide layer of the cells, using the DPCC process wherein the first polysilicon layer is not removed from the transistor area, and the gate regions of the transistors are formed by shorted first and second polysilicon layers. To form the diodes, the polyl layer is removed from the active areas in which the diodes are to be formed, using the same mask employed for shaping polyi; the interpoly dielectric layer and the gate oxide layer are removed from the active areas of the diodes, using the same mask employed for removing the dielectric layer from the transistor area; a second polysilicon layer is deposited directly on to the active areas of the diodes; and the poly2 doping ions penetrate the active areas to form N+ regions which, together with the substrate, constitute the protection diodes. The diodes are thus formed prior to shaping poly2, and are connected to the control gates of the cells by the second polycrystalline silicon layer strips forming the word lines.
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7.发明授权
公开(公告)号：US5793675A
公开(公告)日：1998-08-11
申请号：US829935
申请日：1997-04-01
IPC分类号： G11C17/00 , G11C29/00 , G11C29/50 , G11C29/56 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C29/50004 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/5004 , G11C2029/5006
摘要： A method employing a test structure identical to the memory array whose gate oxide quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is so stressed electrically as to extract electrons from the floating gate of the defective-gate-oxide cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A sub-threshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide of EPROM, EEPROM and flash-EEPROM memories.
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8.发明授权公开(公告)号：US07320904B2
公开(公告)日：2008-01-22
申请号：US11334988
申请日：2006-01-19
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531 , H01L27/11546
摘要： A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.
摘要翻译： 提供了一种用于制造集成在半导体衬底上的电子电路的非活性结构的方法，其中电子电路包括第一和第二电活性结构。 该方法包括将电非电活性结构插入电子电路中以在半导体衬底上方形成均匀的表面。 所述插入包括在所述电非活性结构之中识别与所述第一和第二电活性结构相邻的第一组电非活性结构，以及在所述电非活性结构中识别第二组电非活性结构， 活性结构不与第一和第二电活性结构相邻。 该方法还包括通过不同的光刻步骤在半导体衬底上限定第一和第二组电非活性结构。
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