公开(公告)号：US08938605B2

公开(公告)日：2015-01-20

申请号：US12718685

申请日：2010-03-05

申请人： Fadi Busaba ,  Bruce Giamei ,  David Hutton ,  Eric Schwarz

发明人： Fadi Busaba ,  Bruce Giamei ,  David Hutton ,  Eric Schwarz

IPC分类号： G06F9/30 ,  G06F9/34

CPC分类号： G06F9/342 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30181 ,  G06F9/30189

摘要： A method, information processing system, and computer program product manage instruction execution based on machine state. At least one instruction is received. The at least one instruction is decoded. A current machine state is determined in response to the decoding. The at least one instruction is organized into a set of unit of operations based on the current machine state that has been determined. The set of unit of operations is executed.

摘要翻译： 一种基于机器状态的方法，信息处理系统和计算机程序产品管理指令执行。 至少接收一条指令。 至少一条指令被解码。 响应于解码确定当前机器状态。 基于已经确定的当前机器状态将至少一个指令组织成一组操作单元。 执行一组操作单元。

公开(公告)号：US09104399B2

公开(公告)日：2015-08-11

申请号：US12645716

申请日：2009-12-23

申请人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Christian Jacobi ,  David A. Schroter ,  Eric Schwarz

发明人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Christian Jacobi ,  David A. Schroter ,  Eric Schwarz

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC分类号： G06F9/3001 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3867

摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.

摘要翻译： 一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。 多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。 指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。 指令发布单元向第一执行单元发出第一微操作以产生中间数据。 然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。 在延迟之后，向第二执行单元发出第二个微操作。

公开(公告)号：US20060179290A1

公开(公告)日：2006-08-10

申请号：US11055193

申请日：2005-02-10

申请人： Fadi Busaba ,  Michael Mack ,  John Rell ,  Eric Schwarz ,  Chung-Lung Shum ,  Timothy Slegel ,  Scott Swaney ,  Sheryll Veneracion

发明人： Fadi Busaba ,  Michael Mack ,  John Rell ,  Eric Schwarz ,  Chung-Lung Shum ,  Timothy Slegel ,  Scott Swaney ,  Sheryll Veneracion

IPC分类号： G06F9/44

CPC分类号： G06F9/4812 ,  G06F9/30101 ,  G06F9/3863 ,  G06F2209/481

摘要： A method for creating precise exceptions including checkpointing an exception causing instruction. The checkpointing results in a current checkpointed state. The current checkpointed state is locked. It is determined if any of a plurality of registers require restoration to the current checkpointed state. One or more of the registers are restored to the current checkpointed state in response to the results of the determining indicating that the one or more registers require the restoring. The execution unit is restarted at the exception handler or the next sequential instruction dependent on whether traps are enabled for the exception.

摘要翻译： 一种用于创建精确异常的方法，包括检查指向引起异常的指令。 检查点导致当前检查点状态。 当前检查点状态被锁定。 确定多个寄存器中的任一个是否需要恢复到当前检查点状态。 响应于指示一个或多个寄存器需要恢复的确定结果，一个或多个寄存器恢复到当前检查点状态。 执行单元在异常处理程序或下一个顺序指令下重新启动，取决于是否为异常启用陷阱。

公开(公告)号：US20110154107A1

公开(公告)日：2011-06-23

申请号：US12645771

申请日：2009-12-23

申请人： GREGORY W. ALEXANDER ,  Fadi Busaba ,  David A. Schroter ,  Eric Schwarz ,  Brian W. Thompto ,  Wesley J. Ward, III

发明人： GREGORY W. ALEXANDER ,  Fadi Busaba ,  David A. Schroter ,  Eric Schwarz ,  Brian W. Thompto ,  Wesley J. Ward, III

IPC分类号： G06F11/14 ,  G06F11/07 ,  G06F9/312 ,  G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30189 ,  G06F9/3853 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/004 ,  G06F11/0721 ,  G06F11/0724 ,  G06F11/0751 ,  G06F11/0793

摘要： A method, information processing system, and processor work around a processing flaw in a processor. At least one instruction is fetched from a memory location. The at least one instruction is decoded. An opcode compare operation is compared with the at least one instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw.

摘要翻译： 处理器中的处理缺陷的方法，信息处理系统和处理器。 从存储器位置获取至少一个指令。 至少一条指令被解码。 响应于解码，将操作码比较操作与至少一个操作码比较寄存器中的至少一个指令和一组值进行比较。 该指令用基于操作码比较操作的模式标记。 该模式表示该指令与处理缺陷相关联。

公开(公告)号：US08082467B2

公开(公告)日：2011-12-20

申请号：US12645771

申请日：2009-12-23

申请人： Gregory W. Alexander ,  Fadi Busaba ,  David A. Schroter ,  Eric Schwarz ,  Brian W. Thompto ,  Wesley J. Ward, III

发明人： Gregory W. Alexander ,  Fadi Busaba ,  David A. Schroter ,  Eric Schwarz ,  Brian W. Thompto ,  Wesley J. Ward, III

IPC分类号： G06F11/00

CPC分类号： G06F9/30145 ,  G06F9/30189 ,  G06F9/3853 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/004 ,  G06F11/0721 ,  G06F11/0724 ,  G06F11/0751 ,  G06F11/0793

摘要： A novel system and method for working around a processing flaw in a processor is disclosed. At least one instruction is fetched from a memory location. The instruction is decoded. A set of opcode compare logic, associated with an instruction decode unit and/or a set of global completion table, is used for an opcode compare operation. The compare operation compares the instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw. The pattern is separate and distinct from opcode information within the instruction that is utilized by the set of opcode compare logic during the opcode compare operation.

摘要翻译： 公开了一种用于处理处理器中的处理缺陷的新颖系统和方法。 从存储器位置获取至少一个指令。 该指令被解码。 与指令解码单元和/或一组全局完成表相关联的一组操作码比较逻辑被用于操作码比较操作。 响应于解码，比较操作将指令和至少一个操作码比较寄存器中的一组值进行比较。 该指令用基于操作码比较操作的模式标记。 该模式表示该指令与处理缺陷相关联。 该模式与操作码比较操作期间的一组操作码比较逻辑所使用的指令内的操作码信息分开且不同。

公开(公告)号：US20110153991A1

公开(公告)日：2011-06-23

申请号：US12645716

申请日：2009-12-23

申请人： FADI BUSABA ,  Brian Curran ,  Lee Eisen ,  Christian Jacobi ,  David A. Schroter ,  Eric Schwarz

发明人： FADI BUSABA ,  Brian Curran ,  Lee Eisen ,  Christian Jacobi ,  David A. Schroter ,  Eric Schwarz

IPC分类号： G06F9/312 ,  G06F9/30

CPC分类号： G06F9/3001 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3867

摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.

摘要翻译： 一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。 多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。 指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。 指令发布单元向第一执行单元发出第一微操作以产生中间数据。 然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。 在延迟之后，向第二执行单元发出第二个微操作。

公开(公告)号：US20110154298A1

公开(公告)日：2011-06-23

申请号：US12645687

申请日：2009-12-23

申请人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

发明人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

IPC分类号： G06F9/44

CPC分类号： G06F11/348 ,  G06F11/3409

摘要： A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.

摘要翻译： 一种用处理器收集仪器数据的系统和方法，其中流水线指令执行阶段以无序执行体系结构排列。 全局完成表中的一个指令组被标记为标记组。 存储用于与标记组相关联的处理阶段处理指令的仪表数据。 采样信号脉冲触发确定标记的组是否是下一个完成指令组。 当标记的组是下一个完成组时，当采样脉冲发生时，仪表数据被写为输出。 当标记的组不是下一个到完整的组时发生的采样脉冲期间存在的仪器数据被任选地丢弃。 以等于所需采样率的速率乘以采样脉冲乘以全局完成表中的组数，以更好地确保下一个到完整标记组的发生。

公开(公告)号：US08453124B2

公开(公告)日：2013-05-28

申请号：US12645687

申请日：2009-12-23

申请人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

发明人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

IPC分类号： G06F9/44

CPC分类号： G06F11/348 ,  G06F11/3409

摘要： A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.

摘要翻译： 一种用处理器收集仪器数据的系统和方法，其中流水线指令执行阶段以无序执行体系结构排列。 全局完成表中的一个指令组被标记为标记组。 存储用于与标记组相关联的处理阶段处理指令的仪表数据。 采样信号脉冲触发确定标记的组是否是下一个完成指令组。 当标记的组是下一个完成组时，当采样脉冲发生时，仪表数据被写为输出。 当标记的组不是下一个到完整的组时发生的采样脉冲期间存在的仪器数据被任选地丢弃。 以等于所需采样率的速率乘以采样脉冲乘以全局完成表中的组数，以更好地确保下一个到完整标记组的发生。

公开(公告)号：US20060179090A1

公开(公告)日：2006-08-10

申请号：US11054232

申请日：2005-02-09

申请人： Steven Carlough ,  Bruce Fleischer ,  Wen Li ,  Eric Schwarz

发明人： Steven Carlough ,  Bruce Fleischer ,  Wen Li ,  Eric Schwarz

IPC分类号： G06F7/00

CPC分类号： H03M7/12

摘要： A method for converting from binary to decimal. The method includes receiving a binary number, the binary number including one or more sets of bits. An accumulated sum is set to zero. The accumulated sum is in a binary coded decimal (BCD) format. The following loop is repeated for each set of bits in the binary number in order from the set of bits containing the most significant bit of the binary number to the set of bits containing the least significant bit of the binary number: the accumulated sum is converted into a 5,1 code format resulting in an interim sum. The loop also includes repeating for each next bit in the set in order from the most significant bit to the least significant bit in the set: doubling the interim sum; and replacing the least significant bit of the interim sum with the next bit. The last step in the loop includes converting the interim sum into the BCD format and storing the results of the converting in the accumulated sum. Once all of the sets of bits in the binary number have been processed through the loop, the accumulated sum is output as the final result.

摘要翻译： 一种从二进制转换为十进制的方法。 该方法包括接收二进制数，该二进制数包括一个或多个位组。 累积和设为零。 累加和是二进制编码十进制（BCD）格式。 从包含二进制数的最高有效位的位的集合到包含二进制数的最低有效位的位的位的顺序从二进制数中的每组位重复以下循环：累积和被转换 成为5,1代码格式，产生临时总和。 循环还包括从组中的最高有效位到最低有效位的顺序对集合中的每个下一个位进行重复：使中间和加倍; 并用下一位代替中间和的最低有效位。 循环的最后一步包括将中间和转换为BCD格式，并将转换的结果存储在累加和中。 一旦通过循环处理了二进制数的所有位组，就将输出累加和作为最终结果。

公开(公告)号：US20060179102A1

公开(公告)日：2006-08-10

申请号：US11055221

申请日：2005-02-10

申请人： Steven Carlough ,  Paulomi Kadakia ,  Wen Li ,  Eric Schwarz

发明人： Steven Carlough ,  Paulomi Kadakia ,  Wen Li ,  Eric Schwarz

IPC分类号： G06F7/52

CPC分类号： G06F7/4917 ,  G06F2207/5352

摘要： A method for performing decimal division including receiving a scaled divisor and dividend and storing a subset of the multiples of the scaled divisor. An accumulated quotient is initialized to be equal to zero, a first current remainder is initialized to be equal to the scaled dividend, and a second current remainder is initialized to be equal to the scaled dividend minus the scaled divisor. The following loop is performed until a selected number of quotient digits are produced. An estimated next quotient digit is calculated based on the first digit of the first current remainder. A temp remainder is selected to be either the first current remainder or the second current remainder based on the estimated next quotient digit. A first next remainder is calculated by subtracting one of the stored multiples from the temp remainder, where the stored multiple is selected based on a first digit of the first current remainder. A second next remainder is calculated by subtracting an other one of the stored multiples from the temp remainder, where the other one of the stored multiples is selected based on the first current remainder. An actual quotient digits is calculated based on the estimated next quotient digit, the first current remainder and the first next remainder. The accumulated quotient is updated with the actual next quotient digit. Finally, the first current remainder is set to be equal to the first next remainder and the second current remainder is set to be equal to the second next remainder.