公开(公告)号：US08938605B2

公开(公告)日：2015-01-20

申请号：US12718685

申请日：2010-03-05

申请人： Fadi Busaba ,  Bruce Giamei ,  David Hutton ,  Eric Schwarz

发明人： Fadi Busaba ,  Bruce Giamei ,  David Hutton ,  Eric Schwarz

IPC分类号： G06F9/30 ,  G06F9/34

CPC分类号： G06F9/342 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30181 ,  G06F9/30189

摘要： A method, information processing system, and computer program product manage instruction execution based on machine state. At least one instruction is received. The at least one instruction is decoded. A current machine state is determined in response to the decoding. The at least one instruction is organized into a set of unit of operations based on the current machine state that has been determined. The set of unit of operations is executed.

摘要翻译： 一种基于机器状态的方法，信息处理系统和计算机程序产品管理指令执行。 至少接收一条指令。 至少一条指令被解码。 响应于解码确定当前机器状态。 基于已经确定的当前机器状态将至少一个指令组织成一组操作单元。 执行一组操作单元。

公开(公告)号：US08464030B2

公开(公告)日：2013-06-11

申请号：US12757330

申请日：2010-04-09

申请人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Bruce Giamei ,  David Hutton

发明人： Fadi Busaba ,  Brian Curran ,  Lee Eisen ,  Bruce Giamei ,  David Hutton

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/3017 ,  G06F9/30032 ,  G06F9/30054 ,  G06F9/30058

摘要： A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operation; and the at least one instruction is shortened. The set of unit of operations is then executed.

摘要翻译： 一种方法，信息处理系统和计算机程序产品破解和/或缩短计算机可执行指令。 至少接收一条指令。 至少对指令进行分析。 识别与该至少一条指令相关联的指令类型。 分析指令的基本字段，索引字段，一个或多个操作数和掩码字段中的至少一个。 然后执行以下中的至少一个：将至少一个指令组织成一组操作单元; 并且至少一个指令被缩短。 然后执行一组操作单元。

公开(公告)号：US20070214205A1

公开(公告)日：2007-09-13

申请号：US11749239

申请日：2007-05-16

申请人： Fadi Busaba ,  Steven Carlough ,  David Hutton ,  Christopher Krygowski ,  John Rell ,  Sheryll Veneracion

发明人： Fadi Busaba ,  Steven Carlough ,  David Hutton ,  Christopher Krygowski ,  John Rell ,  Sheryll Veneracion

IPC分类号： G06F7/52

CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

摘要： A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning the multiplicand into a plurality of multiplicand subgroups and at least one of zeroing out of unused bits of the multiplicand subgroup and sign-extending a smaller portion of the multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the plurality of multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the plurality of multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples.

摘要翻译： 在处理设备中实现二进制乘法的方法包括从存储设备获取乘法器和乘法器; 在乘数大于选定长度的情况下，将乘法器分成多个乘法器子组; 在所述被乘数大于所选择的长度的情况下，将所述被乘数划分为多个被乘数的子组和被乘数子组的未使用的比特中的至少一个，并对被乘数子组的较小部分进行符号扩展; 基于所述多个被乘数子组和被乘数中的所选择的被乘数子群中的至少一个，建立多个被乘数; 基于所述多个乘法器子组中的每个乘法器子组来选择所述多个被乘数中的一个或多个被乘数; 以及基于所选择的被乘数生成第一模块化产品。

公开(公告)号：US20130339670A1

公开(公告)日：2013-12-19

申请号：US13524356

申请日：2012-06-15

申请人： Fadi Busaba ,  David Hutton ,  John G. Rell, JR. ,  Chung-Lung K. Shum

发明人： Fadi Busaba ,  David Hutton ,  John G. Rell, JR. ,  Chung-Lung K. Shum

IPC分类号： G06F9/30

CPC分类号： G06F9/3838 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/3834

摘要： Embodiments relate to reducing operand store compare penalties by detecting potential unit of operation (UOP) dependencies. An aspect includes a computer system for reducing operation store compare penalties. The system includes memory and a processor. The system performs a method including cracking an instruction into units of operation, where each UOP includes instruction text and address determination fields. The method includes identifying a load UOP among the plurality of UOPs and comparing values of the address determination fields of the load UOP with values of address determination fields of one or more previously-decoded store UOPs. The method also includes forcing, prior to issuance of the instruction to an execution unit, a dependency between the load UOP and the one or more previously-decoded store UOPs based on the comparing.

摘要翻译： 实施例涉及通过检测潜在的操作单元（UOP）依赖性来减少操作数存储比较处罚。 一方面包括用于减少操作存储比较处罚的计算机系统。 该系统包括内存和处理器。 系统执行包括将指令分解为操作单元的方法，其中每个UOP包括指令文本​​和地址确定字段。 该方法包括识别多个UOP之间的负载UOP，并将负载UOP的地址确定字段的值与一个或多个先前解码的存储UOP的地址确定字段的值进行比较。 该方法还包括在向执行单元发出指令之前强迫基于该比较的加载UOP和一个或多个先前解码的存储UOP之间的依赖关系。

公开(公告)号：US20070233773A1

公开(公告)日：2007-10-04

申请号：US11749224

申请日：2007-05-16

申请人： Fadi Busaba ,  Steven Carlough ,  David Hutton ,  Christopher Krygowski ,  John Rell ,  Sheryll Veneracion

发明人： Fadi Busaba ,  Steven Carlough ,  David Hutton ,  Christopher Krygowski ,  John Rell ,  Sheryll Veneracion

IPC分类号： G06F7/44

CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

摘要： A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.

摘要翻译： 超标量处理器中的二进制乘法系统包括第一流水线，执行单元和第一多路复用器; 与第一流水线和执行单元的一个寄存器通信的第一旋转器; 以及与执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 第二管线，第二执行单元和第二多路复用器; 与所述第二管线的一个寄存器和所述第二执行单元通信的转动器; 以及与第二执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 以及第三管线，与所述第三管道的对寄存器通信的二进制乘法器; 一般登记册; 用于获得第一和第二操作数的操作数缓冲器; 和一条总线，用于管道，通用寄存器和操作数缓冲区之间的通信。

公开(公告)号：US09626189B2

公开(公告)日：2017-04-18

申请号：US13524356

申请日：2012-06-15

申请人： Fadi Busaba ,  David Hutton ,  John G. Rell, Jr. ,  Chung-Lung K. Shum

发明人： Fadi Busaba ,  David Hutton ,  John G. Rell, Jr. ,  Chung-Lung K. Shum

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3838 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/3834

摘要： Embodiments relate to reducing operand store compare penalties by detecting potential unit of operation (UOP) dependencies. An aspect includes a computer system for reducing operation store compare penalties. The system includes memory and a processor. The system performs a method including cracking an instruction into units of operation, where each UOP includes instruction text and address determination fields. The method includes identifying a load UOP among the plurality of UOPs and comparing values of the address determination fields of the load UOP with values of address determination fields of one or more previously-decoded store UOPs. The method also includes forcing, prior to issuance of the instruction to an execution unit, a dependency between the load UOP and the one or more previously-decoded store UOPs based on the comparing.

公开(公告)号：US20110154298A1

公开(公告)日：2011-06-23

申请号：US12645687

申请日：2009-12-23

申请人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

发明人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

IPC分类号： G06F9/44

CPC分类号： G06F11/348 ,  G06F11/3409

摘要： A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.

摘要翻译： 一种用处理器收集仪器数据的系统和方法，其中流水线指令执行阶段以无序执行体系结构排列。 全局完成表中的一个指令组被标记为标记组。 存储用于与标记组相关联的处理阶段处理指令的仪表数据。 采样信号脉冲触发确定标记的组是否是下一个完成指令组。 当标记的组是下一个完成组时，当采样脉冲发生时，仪表数据被写为输出。 当标记的组不是下一个到完整的组时发生的采样脉冲期间存在的仪器数据被任选地丢弃。 以等于所需采样率的速率乘以采样脉冲乘以全局完成表中的组数，以更好地确保下一个到完整标记组的发生。

公开(公告)号：US08453124B2

公开(公告)日：2013-05-28

申请号：US12645687

申请日：2009-12-23

申请人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

发明人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

IPC分类号： G06F9/44

CPC分类号： G06F11/348 ,  G06F11/3409

摘要： A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.

摘要翻译： 一种用处理器收集仪器数据的系统和方法，其中流水线指令执行阶段以无序执行体系结构排列。 全局完成表中的一个指令组被标记为标记组。 存储用于与标记组相关联的处理阶段处理指令的仪表数据。 采样信号脉冲触发确定标记的组是否是下一个完成指令组。 当标记的组是下一个完成组时，当采样脉冲发生时，仪表数据被写为输出。 当标记的组不是下一个到完整的组时发生的采样脉冲期间存在的仪器数据被任选地丢弃。 以等于所需采样率的速率乘以采样脉冲乘以全局完成表中的组数，以更好地确保下一个到完整标记组的发生。

公开(公告)号：US20070174554A1

公开(公告)日：2007-07-26

申请号：US11339196

申请日：2006-01-25

申请人： David Hutton ,  Kathryn Jackson ,  Keith Langston ,  Pak-kin Mak ,  Chung-Lung Shum

发明人： David Hutton ,  Kathryn Jackson ,  Keith Langston ,  Pak-kin Mak ,  Chung-Lung Shum

IPC分类号： G06F12/00

CPC分类号： G06F12/0815 ,  G06F12/0811 ,  G06F12/12

摘要： Caching where portions of data are stored in slower main memory and are transferred to faster memory between one or more processors and the main memory. The cache is such that an individual cache system must communicate to other associated cache systems, or check with such cache systems, to determine if they contain a copy of a given cached location prior to or upon modification or appropriation of data at a given cached location. The cache further includes provisions for determining when the data stored in a particular memory location may be replaced.

摘要翻译： 缓存数据的一部分存储在较慢的主存储器中，并被传送到一个或多个处理器与主存储器之间的更快的存储器。 高速缓存使得单个高速缓存系统必须与其他相关联的高速缓存系统通信，或者与这种高速缓存系统进行检查，以确定它们是否在给定的高速缓存位置修改或占用数据之前或之后包含给定缓存位置的副本 。 高速缓存还包括用于确定何时可以替换存储在特定存储器位置中的数据的规定。

公开(公告)号：US08406793B2

公开(公告)日：2013-03-26

申请号：US12658611

申请日：2010-02-09

申请人： Nick Russell ,  Peter Dawes ,  David Hutton

发明人： Nick Russell ,  Peter Dawes ,  David Hutton

IPC分类号： H04W4/00

CPC分类号： H04L51/30 ,  H04L51/38 ,  H04W4/12

摘要： An apparatus for delivering a message from an originating subscriber to a target subscriber across a communication network comprising; means for receiving in a first network a message from an originating subscriber to a target subscriber and an identifier of the target subscriber, the target subscriber being associated with the first network and the originating subscriber being associated with a second network, the message and identifier being received from the second network; means for identifying at least one network node associated with the target subscriber and being responsible for delivering messages to the target subscriber; means for selecting a network node from the at least one network node for delivery of the message; means for receiving from the second network an allowed time period for delivery of the message; means for determining the expected delivery time of the message for the selected network node; means for comparing the expected delivery time with the allowed time period for delivery; and means for forwarding the message to the selected network node for delivery to the target subscriber in dependence on the allowed time period exceeding the expected delivery time.

摘要翻译： 一种用于经由通信网络将消息从始发用户传送到目标用户的装置，包括： 用于在第一网络中接收从始发用户到目标用户的消息和目标用户的标识符的装置，所述目标用户与所述第一网络相关联，所述始发用户与第二网络相关联，所述消息和标识符是 从第二个网络接收; 用于识别与所述目标订户相关联的至少一个网络节点并且负责将消息传递到所述目标订户的装置; 用于从所述至少一个网络节点选择用于传递所述消息的网络节点的装置; 用于从所述第二网络接收用于传送所述消息的允许时间段的装置; 用于确定所选网络节点的消息的预期传送时间的装置; 用于将预期交付时间与允许的交货时间进行比较的手段; 以及用于将消息转发到所选择的网络节点以根据超过预期递送时间的允许时间段传送到目标用户的装置。