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公开(公告)号：US07646083B2
公开(公告)日：2010-01-12
申请号：US12059526
申请日：2008-03-31
申请人： Fan Yeung , Sam Ziqun Zhao , Nir Matalon , Victor Fong
发明人： Fan Yeung , Sam Ziqun Zhao , Nir Matalon , Victor Fong
IPC分类号： H01L23/495
CPC分类号： H01L23/49541 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/32245 , H01L2224/45111 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45155 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The die is attached to the die-attach paddle. The encapsulating material encapsulates the die on the die-attach paddle, encapsulates bond wires connected between the die and the pins, and fills a space between the pins and the die-attach paddle. One or more of the pins are extended. An extended pin may be elongated, L shaped, T shaped, or “wishbone” shaped. The extended pin(s) enable wire bonding of additional ground, power, and I/O (input/output) pads of the die in a manner that does not significantly increase QFN package cost.
摘要翻译： 提供了集成电路封装和引线框架的方法，系统和装置。 四平面无引线（QFN）封装包括多个外围定位的引脚，管芯附着的焊盘，集成电路管芯和封装材料。 管芯附着板定位在由销形成的周边内。 模具连接到管芯附接板上。 封装材料将管芯封装在管芯附着的焊盘上，封装连接在管芯和引脚之间的接合线，并且填充管脚和管芯附接焊盘之间的空间。 一个或多个引脚被扩展。 延伸的销可以是细长的，L形的，T形的或“叉形”的形状。 扩展引脚可以以不显着增加QFN封装成本的方式实现管芯附加接地，电源和I / O（输入/输出）焊盘的引线接合。
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公开(公告)号：US20090243054A1
公开(公告)日：2009-10-01
申请号：US12059526
申请日：2008-03-31
申请人： Fan Yeung , Sam Ziqun Zhao , Nir Matalon , Victor Fong
发明人： Fan Yeung , Sam Ziqun Zhao , Nir Matalon , Victor Fong
IPC分类号： H01L23/495 , H05K7/18 , H01L21/56
CPC分类号： H01L23/49541 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/32245 , H01L2224/45111 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45155 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The die is attached to the die-attach paddle. The encapsulating material encapsulates the die on the die-attach paddle, encapsulates bond wires connected between the die and the pins, and fills a space between the pins and the die-attach paddle. One or more of the pins are extended. An extended pin may be elongated, L shaped, T shaped, or “wishbone” shaped. The extended pin(s) enable wire bonding of additional ground, power, and I/O (input/output) pads of the die in a manner that does not significantly increase QFN package cost.
摘要翻译： 提供了集成电路封装和引线框架的方法，系统和装置。 四平面无引线（QFN）封装包括多个外围定位的引脚，管芯附着的焊盘，集成电路管芯和封装材料。 管芯附着板定位在由销形成的周边内。 模具连接到管芯附接板上。 封装材料将管芯封装在管芯附着的焊盘上，封装连接在管芯和引脚之间的接合线，并且填充管脚和管芯附接焊盘之间的空间。 一个或多个引脚被扩展。 延伸的销可以是细长的，L形的，T形的或“叉形”的形状。 扩展引脚可以以不显着增加QFN封装成本的方式实现管芯附加接地，电源和I / O（输入/输出）焊盘的引线接合。
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公开(公告)号：US20090278264A1
公开(公告)日：2009-11-12
申请号：US12119174
申请日：2008-05-12
申请人： Roden R. Topacio , Vincent Chan , Fan Yeung
发明人： Roden R. Topacio , Vincent Chan , Fan Yeung
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H05K3/3452 , H01L23/49811 , H01L23/49816 , H01L23/50 , H01L24/16 , H01L24/81 , H01L2224/05571 , H01L2224/05573 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/13099 , H01L2224/13111 , H01L2224/16237 , H01L2224/81136 , H01L2224/81801 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H05K2201/0989 , H05K2201/10674 , H01L2924/00014
摘要： Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.
摘要翻译： 公开了各种半导体芯片封装及其制造方法。 在一个方面，提供了一种制造方法，其包括将焊料凸点耦合到半导体芯片的一侧，并使焊料凸块与耦合到基板的导体焊盘接触并定位在衬底上的焊料掩模的开口中 。 导体垫具有第一横向尺寸，并且开口具有大于第一横向尺寸的第二横向尺寸。 在焊料凸块和导体焊盘之间建立冶金结合。
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公开(公告)号：US08779598B2
公开(公告)日：2014-07-15
申请号：US13170820
申请日：2011-06-28
IPC分类号： H01L21/00 , H01L21/30 , H01L21/4763 , H01L23/52
CPC分类号： H01L21/6835 , H01L21/4857 , H01L23/145 , H01L23/49827 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2221/68345 , H01L2221/68381 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H01L2924/00014 , H01L2924/12042 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments described herein provide a method of manufacturing integrated circuit (IC) devices. The method includes coupling a first surface of a first intermediate substrate to a first surface of a second intermediate substrate, forming a first plurality of patterned metal layers on a second surface of the first intermediate substrate to form a first substrate and a second plurality of patterned metal layers on a second surface of the second intermediate substrate to form a second substrate, and separating the first and second substrates. Each of the first substrate and the second substrate is configured to facilitate electrical interconnection between a respective IC die and a respective printed circuit board (PCB).
摘要翻译： 本文描述的实施例提供了一种制造集成电路（IC）装置的方法。 该方法包括将第一中间衬底的第一表面耦合到第二中间衬底的第一表面，在第一中间衬底的第二表面上形成第一多个图案化金属层以形成第一衬底和第二多个图案化 在第二中间基板的第二表面上的金属层，以形成第二基板，并分离第一和第二基板。 第一基板和第二基板中的每一个被配置为便于相应的IC管芯和相应的印刷电路板（PCB）之间的电互连。
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公开(公告)号：US20100140798A1
公开(公告)日：2010-06-10
申请号：US12692239
申请日：2010-01-22
申请人： Roden R. Topacio , Vincent Chan , Fan Yeung
发明人： Roden R. Topacio , Vincent Chan , Fan Yeung
IPC分类号： H01L23/498
CPC分类号： H05K3/3452 , H01L23/49811 , H01L23/49816 , H01L23/50 , H01L24/16 , H01L24/81 , H01L2224/05571 , H01L2224/05573 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/13099 , H01L2224/13111 , H01L2224/16237 , H01L2224/81136 , H01L2224/81801 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H05K2201/0989 , H05K2201/10674 , H01L2924/00014
摘要： Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.
摘要翻译： 公开了各种半导体芯片封装及其制造方法。 在一个方面，提供了一种制造方法，其包括将焊料凸点耦合到半导体芯片的一侧，并使焊料凸块与耦合到基板的导体焊盘接触并定位在衬底上的焊料掩模的开口中 。 导体垫具有第一横向尺寸，并且开口具有大于第一横向尺寸的第二横向尺寸。 在焊料凸块和导体焊盘之间建立冶金结合。
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公开(公告)号：US08378471B2
公开(公告)日：2013-02-19
申请号：US12692239
申请日：2010-01-22
申请人： Roden R. Topacio , Vincent Chan , Fan Yeung
发明人： Roden R. Topacio , Vincent Chan , Fan Yeung
IPC分类号： H01L23/02
CPC分类号： H05K3/3452 , H01L23/49811 , H01L23/49816 , H01L23/50 , H01L24/16 , H01L24/81 , H01L2224/05571 , H01L2224/05573 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/13099 , H01L2224/13111 , H01L2224/16237 , H01L2224/81136 , H01L2224/81801 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H05K2201/0989 , H05K2201/10674 , H01L2924/00014
摘要： Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.
摘要翻译： 公开了各种半导体芯片封装及其制造方法。 在一个方面，提供了一种制造方法，其包括将焊料凸点耦合到半导体芯片的一侧，并使焊料凸块与耦合到基板的导体焊盘接触并定位在衬底上的焊料掩模的开口中 。 导体垫具有第一横向尺寸，并且开口具有大于第一横向尺寸的第二横向尺寸。 在焊料凸块和导体焊盘之间建立冶金结合。
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公开(公告)号：US07670939B2
公开(公告)日：2010-03-02
申请号：US12119174
申请日：2008-05-12
申请人： Roden R. Topacio , Vincent Chan , Fan Yeung
发明人： Roden R. Topacio , Vincent Chan , Fan Yeung
IPC分类号： H01L21/44
CPC分类号： H05K3/3452 , H01L23/49811 , H01L23/49816 , H01L23/50 , H01L24/16 , H01L24/81 , H01L2224/05571 , H01L2224/05573 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/13099 , H01L2224/13111 , H01L2224/16237 , H01L2224/81136 , H01L2224/81801 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H05K2201/0989 , H05K2201/10674 , H01L2924/00014
摘要： Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.
摘要翻译： 公开了各种半导体芯片封装及其制造方法。 在一个方面，提供了一种制造方法，其包括将焊料凸点耦合到半导体芯片的一侧，并使焊料凸块与耦合到基板的导体焊盘接触并定位在衬底上的焊料掩模的开口中 。 导体垫具有第一横向尺寸，并且开口具有大于第一横向尺寸的第二横向尺寸。 在焊料凸块和导体焊盘之间建立冶金结合。
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