公开(公告)号：US07646083B2

公开(公告)日：2010-01-12

申请号：US12059526

申请日：2008-03-31

申请人： Fan Yeung ,  Sam Ziqun Zhao ,  Nir Matalon ,  Victor Fong

发明人： Fan Yeung ,  Sam Ziqun Zhao ,  Nir Matalon ,  Victor Fong

IPC分类号： H01L23/495

CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The die is attached to the die-attach paddle. The encapsulating material encapsulates the die on the die-attach paddle, encapsulates bond wires connected between the die and the pins, and fills a space between the pins and the die-attach paddle. One or more of the pins are extended. An extended pin may be elongated, L shaped, T shaped, or “wishbone” shaped. The extended pin(s) enable wire bonding of additional ground, power, and I/O (input/output) pads of the die in a manner that does not significantly increase QFN package cost.

摘要翻译： 提供了集成电路封装和引线框架的方法，系统和装置。 四平面无引线（QFN）封装包括多个外围定位的引脚，管芯附着的焊盘，集成电路管芯和封装材料。 管芯附着板定位在由销形成的周边内。 模具连接到管芯附接板上。 封装材料将管芯封装在管芯附着的焊盘上，封装连接在管芯和引脚之间的接合线，并且填充管脚和管芯附接焊盘之间的空间。 一个或多个引脚被扩展。 延伸的销可以是细长的，L形的，T形的或“叉形”的形状。 扩展引脚可以以不显着增加QFN封装成本的方式实现管芯附加接地，电源和I / O（输入/输出）焊盘的引线接合。

公开(公告)号：US20090243054A1

公开(公告)日：2009-10-01

申请号：US12059526

申请日：2008-03-31

申请人： Fan Yeung ,  Sam Ziqun Zhao ,  Nir Matalon ,  Victor Fong

发明人： Fan Yeung ,  Sam Ziqun Zhao ,  Nir Matalon ,  Victor Fong

IPC分类号： H01L23/495 ,  H05K7/18 ,  H01L21/56

CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The die is attached to the die-attach paddle. The encapsulating material encapsulates the die on the die-attach paddle, encapsulates bond wires connected between the die and the pins, and fills a space between the pins and the die-attach paddle. One or more of the pins are extended. An extended pin may be elongated, L shaped, T shaped, or “wishbone” shaped. The extended pin(s) enable wire bonding of additional ground, power, and I/O (input/output) pads of the die in a manner that does not significantly increase QFN package cost.

摘要翻译： 提供了集成电路封装和引线框架的方法，系统和装置。 四平面无引线（QFN）封装包括多个外围定位的引脚，管芯附着的焊盘，集成电路管芯和封装材料。 管芯附着板定位在由销形成的周边内。 模具连接到管芯附接板上。 封装材料将管芯封装在管芯附着的焊盘上，封装连接在管芯和引脚之间的接合线，并且填充管脚和管芯附接焊盘之间的空间。 一个或多个引脚被扩展。 延伸的销可以是细长的，L形的，T形的或“叉形”的形状。 扩展引脚可以以不显着增加QFN封装成本的方式实现管芯附加接地，电源和I / O（输入/输出）焊盘的引线接合。

公开(公告)号：US09772880B2

公开(公告)日：2017-09-26

申请号：US12877729

申请日：2010-09-08

申请人： Ahmadreza (Reza) Rofougaran ,  Arya Reza Behzad ,  Sam Ziqun Zhao ,  Jesus Alfonso Castaneda ,  Michael Boers

发明人： Ahmadreza (Reza) Rofougaran ,  Arya Reza Behzad ,  Sam Ziqun Zhao ,  Jesus Alfonso Castaneda ,  Michael Boers

IPC分类号： H04W80/04 ,  G06F9/50 ,  H04B7/10 ,  H04B5/00 ,  H04W4/00 ,  H04W84/18 ,  H04B7/26

CPC分类号： G06F9/50 ,  H04B5/0037 ,  H04B7/10 ,  H04B7/26 ,  H04W4/80 ,  H04W84/18 ,  Y10T307/492

摘要： Embodiments of the present invention are directed to a wireless bus for intra-chip and inter-chip communication having adaptable links and routes among wireless-enabled components (WECs) of the wireless bus. Links and routes may be adapted according to one or more of, among other factors, the relative position of WECs, available capabilities (e.g., communication capabilities) at WECs, availability of resources at WECs, and the physical environment.

公开(公告)号：US09209508B2

公开(公告)日：2015-12-08

申请号：US13248787

申请日：2011-09-29

申请人： Ahmadreza Rofougaran ,  Arya Reza Behzad ,  Sam Ziqun Zhao ,  Jesus Alfonso Castaneda ,  Michael Boers

发明人： Ahmadreza Rofougaran ,  Arya Reza Behzad ,  Sam Ziqun Zhao ,  Jesus Alfonso Castaneda ,  Michael Boers

IPC分类号： H01P1/18 ,  H01P1/06 ,  H01P3/00 ,  H01L23/522 ,  H01L23/66 ,  H01L25/065 ,  B81B7/00 ,  H01L41/09 ,  H01H59/00

摘要： Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

公开(公告)号：US09041192B2

公开(公告)日：2015-05-26

申请号：US13598291

申请日：2012-08-29

申请人： Seyed Mahdi Saeidi ,  Sam Ziqun Zhao

发明人： Seyed Mahdi Saeidi ,  Sam Ziqun Zhao

IPC分类号： H01L23/34 ,  H01L21/50 ,  H01L23/16 ,  H01L23/42 ,  H01L23/367

CPC分类号： H01L23/3675 ,  H01L21/52 ,  H01L23/16 ,  H01L23/42 ,  H01L23/562 ,  H01L24/33 ,  H01L2224/16225 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/29076 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33051 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3511 ,  H01L2924/00

摘要： Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.

摘要翻译： 描述了包括两个或更多个热界面材料（TIM）的翻转芯片封装。 通过焊料凸块将裸片安装到基板上。 第一个TIM应用于管芯，并具有第一个热阻。 第二TIM施加到管芯和/或衬底，并且具有大于第一热阻的第二热阻。 散热器盖的开口端安装到基板上，使得模具定位在由散热器盖和基板形成的外壳中。 第一TIM和第二TIM分别与散热器盖的内表面接触。 环形加强件可以围绕模具并且通过第二TIM连接在基板和散热器盖之间。

公开(公告)号：US08971806B2

公开(公告)日：2015-03-03

申请号：US12877723

申请日：2010-09-08

申请人： Ahmadreza (Reza) Rofougaran ,  Arya Reza Behzad ,  Sam Ziqun Zhao ,  Jesus Alfonso Castaneda ,  Michael Boers

发明人： Ahmadreza (Reza) Rofougaran ,  Arya Reza Behzad ,  Sam Ziqun Zhao ,  Jesus Alfonso Castaneda ,  Michael Boers

IPC分类号： H04B7/00 ,  G06F13/42 ,  H04B7/10 ,  G06F13/364 ,  H04W84/18

CPC分类号： G06F9/50 ,  H04B5/0037 ,  H04B7/10 ,  H04B7/26 ,  H04W4/80 ,  H04W84/18 ,  Y10T307/492

摘要： Embodiments of the present invention are directed to a scalable wireless bus for intra-chip and inter-chip communication. The scalable wireless bus includes a plurality of wireless-enabled components (WECs). In an embodiment, the scalable wireless bus may have at least one of the number of links among WECs and the capacity of said links adapted based on one or more factors. For example, the number of links and the capacity of the links may be adapted according to one or more of, among other factors, expected activity level over the wireless bus, desired power consumption, delay, and interference levels.

摘要翻译： 本发明的实施例涉及用于片内和芯片间通信的可扩展无线总线。 可扩展无线总线包括多个无线使能组件（WEC）。 在一个实施例中，可扩展无线总线可以具有基于一个或多个因素的WEC之间的链路数量和所述链路的容量中的至少一个链路。 例如，链路的数量和链路的容量可以根据无线总线上的预期活动级别，期望的功率消耗，延迟和干扰级别中的一个或多个来调整。

公开(公告)号：US08718550B2

公开(公告)日：2014-05-06

申请号：US13247543

申请日：2011-09-28

申请人： Sam Ziqun Zhao ,  Rezaur Rahman Khan

发明人： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC分类号： H04B5/00

CPC分类号： H01L23/34 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/50 ,  H01L23/552 ,  H01L24/73 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H04B1/40 ,  H04B5/0037 ,  H04B5/0068 ,  H04B7/0617 ,  H01L2924/00012 ,  H01L2924/00

摘要： Embodiments of an interposer package structure are provided herein. Embodiments include a substrate having first and second opposing surfaces. An IC die electrically coupled to the first surface of the substrate. A plurality of contact members coupled to the first surface of the substrate. An interposer having a plurality of contact elements located on a first surface. Each conductive element coupled to a respective one of the plurality of contact members. The interposer is configured to facilitate wireless communication between the IC die and another device, heat spreading and electromagnetic interference shielding.

摘要翻译： 本文提供了插入器封装结构的实施例。 实施例包括具有第一和第二相对表面的基板。 一个电连接到该衬底的第一表面的IC管芯。 耦合到所述基板的第一表面的多个接触构件。 具有位于第一表面上的多个接触元件的插入件。 每个导电元件连接到多个接触元件中的相应一个。 插入器被配置为促进IC管芯与另一器件之间的无线通信，热扩散和电磁干扰屏蔽。

公开(公告)号：US20130221499A1

公开(公告)日：2013-08-29

申请号：US13405721

申请日：2012-02-27

申请人： Sampath K.V. Karikalan ,  Kevin Kunzhong Hu ,  Sam Ziqun Zhao ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

发明人： Sampath K.V. Karikalan ,  Kevin Kunzhong Hu ,  Sam Ziqun Zhao ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC分类号： H01L23/552

CPC分类号： H01L25/0657 ,  H01L23/147 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/552 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19107 ,  H01L2924/3025

摘要： There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.

摘要翻译： 这里公开了位于顶部有源管芯和底部有源管芯之间的屏蔽插入器的各种实现方式，用于屏蔽活动管芯免受电磁噪声。 一种实现方式包括内插器电介质层，内插电介质层内的穿硅通孔（TSV）和电磁屏蔽。 TSV将电磁屏蔽连接到第一固定电位。 电磁屏蔽可以包括横跨屏蔽插入件横向延伸的导电层格。 屏蔽插入器还可以包括连接到另一个固定电位的另一个电磁屏蔽。

公开(公告)号：US20130214408A1

公开(公告)日：2013-08-22

申请号：US13401077

申请日：2012-02-21

申请人： Sam Ziqun Zhao ,  Rezaur Rahman Khan

发明人： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC分类号： H01L23/498 ,  H05K1/09 ,  B23K31/02 ,  H05K1/11

CPC分类号： H01L21/486 ,  B23K1/0016 ,  B23K3/08 ,  B23K2101/40 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/4985 ,  H01L2224/16225

摘要： There are disclosed herein various implementations of an interposer for use in semiconductor packaging. One exemplary implementation comprises a conductive post formed from a wire bond. A first end of the conductive post is mechanically joined to a conductive pad on a first surface of the interposer, while a second end of the conductive post is capable of making electrical connection to a contact body on an active surface of a semiconductor die. Such an interposer may include a rigid or flexible interposer dielectric. In one exemplary implementation, the interposer dielectric has a via formed therein, the conductive post being situated in the via and extending through a second surface of the interposer opposite the first surface.

摘要翻译： 这里公开了用于半导体封装的插入件的各种实施方案。 一个示例性实施例包括由引线接合形成的导电柱。 导电柱的第一端机械连接到插入件的第一表面上的导电焊盘，而导电柱的第二端能够与半导体管芯的有源表面上的接触体电连接。 这样的插入件可以包括刚性或柔性插入物电介质。 在一个示例性实施例中，插入器电介质具有形成在其中的通孔，导电柱位于通孔中并延伸穿过与第一表面相对的插入件的第二表面。

公开(公告)号：US20130154106A1

公开(公告)日：2013-06-20

申请号：US13325951

申请日：2011-12-14

申请人： Kevin Kunzhong Hu ,  Sam Ziqun Zhao ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Sampath K.V. Karikalan ,  Xiangdong Chen

发明人： Kevin Kunzhong Hu ,  Sam Ziqun Zhao ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Sampath K.V. Karikalan ,  Xiangdong Chen

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L25/105 ,  H01L21/50 ,  H01L21/78 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/821 ,  H01L2224/83 ,  H01L2224/9202 ,  H01L2224/92133 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.

摘要翻译： 本公开的示例性实施方案包括具有来自位于底部重构晶片的底模上方的顶部重构晶片的顶模的堆叠封装。 顶部模具和底部模具通过绝缘装置彼此绝缘。 顶模和底模也通过绝缘装置互连。 绝缘装置可以包括在顶模侧面的顶部模塑料和位于底模侧面的底部模塑料。 顶部模具和底部模具可以通过至少顶部模塑料相互连接。 此外，顶模和底模可以通过在绝缘装置内延伸的导电通孔相互连接。