公开(公告)号：US09564391B2

公开(公告)日：2017-02-07

申请号：US13030470

申请日：2011-02-18

Applicant: Kevin (Kunzhong) Hu ,  Edward Law

Inventor： Kevin (Kunzhong) Hu ,  Edward Law

IPC: H01L23/498 ,  H01L23/36 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/36 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: An integrated circuit (IC) device is provided. The IC device includes an IC die having opposing first and second surfaces, a carrier coupled to the first surface of the IC die, a laminate coupled to the carrier and the second surface of the IC die, and a trace located on a surface of the laminate and electrically coupled to a bond pad located on the second surface of the IC die. The trace is configured to couple the bond pad to a circuit board.

Abstract translation: 提供集成电路（IC）装置。 IC器件包括具有相对的第一和第二表面的IC管芯，耦合到IC管芯的第一表面的载体，耦合到载体和IC管芯的第二表面的层压体，以及位于IC芯片的表面上的迹线 层压并电耦合到位于IC芯片的第二表面上的接合焊盘。 轨迹被配置为将接合焊盘耦合到电路板。

公开(公告)号：US20110318885A1

公开(公告)日：2011-12-29

申请号：US13224933

申请日：2011-09-02

Applicant: Sam Ziqun Zhao ,  Reaz-ur Rahman Khan ,  Edward Law ,  Marc Papageorge

Inventor： Sam Ziqun Zhao ,  Reaz-ur Rahman Khan ,  Edward Law ,  Marc Papageorge

IPC: H01L21/56 ,  H01L21/60

CPC classification number: H01L24/48 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/484 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In one embodiment, a method for assembling a ball grid array (BGA) package is provided. The method includes providing a stiffener that has opposing first and second surfaces, wherein the first surface is capable of mounting an integrated circuit (IC) die in a central area and forming a pattern in at least a portion of the first surface to enhance the adhesiveness of an encapsulant material to the first surface.

Abstract translation: 在一个实施例中，提供了一种用于组装球栅阵列（BGA）封装的方法。 该方法包括提供具有相对的第一和第二表面的加强件，其中第一表面能够将集成电路（IC）模具安装在中心区域中并且在第一表面的至少一部分中形成图案以增强粘合性 的密封剂材料。

公开(公告)号：US20100052151A1

公开(公告)日：2010-03-04

申请号：US12619385

申请日：2009-11-16

Applicant: Sam Ziqun ZHAO ,  Reza-ur Rahman Khan ,  Edward Law ,  Marc Papageorge

Inventor： Sam Ziqun ZHAO ,  Reza-ur Rahman Khan ,  Edward Law ,  Marc Papageorge

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L24/48 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/484 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Electrically and thermally enhanced die-up ball grid array (BGA) packages are described. A BGA package includes a stiffener, substrate, a silicon die, and solder balls. The die is mounted to the top of the stiffener. The stiffener is mounted to the top of the substrate. A plurality of solder balls are attached to the bottom surface of the substrate. A top surface of the stiffener may be patterned. A second stiffener may be attached to the first stiffener. The substrate may include one, two, four, or other number of metal layers. Conductive vias through a dielectric layer of the substrate may couple the stiffener to solder balls. An opening may be formed through the substrate, exposing a portion of the stiffener. The stiffener may have a down-set portion. A heat slug may be attached to the exposed portion of the stiffener. A locking mechanism may be used to enhance attachment of the heat slug to the stiffener. The heat slug may be directly attached to the die through an opening in the stiffener.

Abstract translation: 描述了电热和热增强型压焊球栅阵列（BGA）封装。 BGA封装包括加强件，衬底，硅管芯和焊球。 模具安装在加强筋的顶部。 加强件安装到基板的顶部。 多个焊球附着在基板的底面上。 加强件的顶表面可以被图案化。 第二加强件可以附接到第一加强件。 衬底可以包括一个，两个，四个或其它数量的金属层。 通过基底的电介质层的导电孔可将加强件耦合到焊球。 可以通过基板形成开口，暴露加强件的一部分。 加强件可以具有下降部分。 散热片可以附着在加强件的暴露部分上。 可以使用锁定机构来增强热块与加强件的连接。 热芯可以通过加强件中的开口直接附接到模具。

公开(公告)号：US20080096312A1

公开(公告)日：2008-04-24

申请号：US11583719

申请日：2006-10-20

Applicant: Edward Law ,  Sam Ziqun Zhao ,  Rezaur Rahman Khan

Inventor： Edward Law ,  Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L21/00

CPC classification number: H01L23/3128 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48465 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85005 ,  H01L2224/9222 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/11 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods and apparatuses for improved thermal, electrical and/or mechanical performance in integrated circuit (IC) packages are described. An IC circuit package comprises a substrate having a central opening. An IC die, resides within the opening in the substrate. Wirebonds couples a plurality of bond pads on a top surface of the IC die to a plurality of bond fingers on a top surface the substrate. An encapsulating material encapsulates at least the IC die and the wirebonds such that at least a bottom surface of the IC die is left exposed. The encapsulating material suspends the die such that at least a portion of the die is held within the opening in the substrate.

Abstract translation: 描述了用于改善集成电路（IC）封装中的热，电和/或机械性能的方法和装置。 IC电路封装包括具有中心开口的基板。 IC芯片位于基板的开口内。 导线将IC芯片的顶表面上的多个接合焊盘耦合到衬底的顶表面上的多个接合指状物。 封装材料至少封装IC芯片和引线键，使得IC芯片的至少底面露出。 封装材料悬挂模具，使得模具的至少一部分保持在基板的开口内。

公开(公告)号：US20050258216A1

公开(公告)日：2005-11-24

申请号：US10850934

申请日：2004-05-20

Applicant: Dean Kossives ,  Kambhampati Ramakrishna ,  Edward Law ,  Diane Sahakian ,  Theodore Tessier ,  Jamin Ling

Inventor： Dean Kossives ,  Kambhampati Ramakrishna ,  Edward Law ,  Diane Sahakian ,  Theodore Tessier ,  Jamin Ling

IPC: G02B6/30

CPC classification number: H01L27/14618 ,  H01L27/14625 ,  H01L27/14683 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: An optoelectronic sensor is attached to an optically transparent substrate, such as glass, and encapsulated to form an optoelectronic device. An optical assembly can be mounted opposite the optoelectronic sensor. Filters and refractive index matching materials may be included between the optoelectronic sensor and the optically transparent substrate.

Abstract translation: 光电传感器附着在诸如玻璃之类的光学透明衬底上，并被封装以形成光电器件。 光学组件可以安装在光电传感器的对面。 滤光器和折射率匹配材料可以包括在光电传感器和光学透明衬底之间。

公开(公告)号：US06882042B2

公开(公告)日：2005-04-19

申请号：US09997272

申请日：2001-11-30

Applicant: Sam Ziqun Zhao ,  Reaz-ur Rahman Khan ,  Edward Law ,  Marc Papageorge

Inventor： Sam Ziqun Zhao ,  Reaz-ur Rahman Khan ,  Edward Law ,  Marc Papageorge

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/433 ,  H01L23/498 ,  H01L23/10 ,  H01L23/34

CPC classification number: H01L24/48 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/484 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Electrically and thermally enhanced die-up ball grid array (BGA) packages are described. A BGA package includes a stiffener, substrate, a silicon die, and solder balls. The die is mounted to the top of the stiffener. The stiffener is mounted to the top of the substrate. A plurality of solder balls are attached to the bottom surface of the substrate. A top surface of the stiffener may be patterned. A second stiffener may be attached to the first stiffener. The substrate may include one, two, four, or other number of metal layers. Conductive vias through a dielectric layer of the substrate may couple the stiffener to solder balls. An opening may be formed through the substrate, exposing a portion of the stiffener. The stiffener may have a down-set portion. A heat slug may be attached to the exposed portion of the stiffener. A locking mechanism may be used to enhance attachment of the heat slug to the stiffener. The heat slug may be directly attached to the die through an opening in the stiffener.

Abstract translation: 描述了电热和热增强型压焊球栅阵列（BGA）封装。 BGA封装包括加强件，衬底，硅管芯和焊球。 模具安装在加强筋的顶部。 加强件安装到基板的顶部。 多个焊球附着在基板的底面上。 加强件的顶表面可以被图案化。 第二加强件可以附接到第一加强件。 衬底可以包括一个，两个，四个或其它数量的金属层。 通过基底的电介质层的导电孔可将加强件耦合到焊球。 可以通过基板形成开口，暴露加强件的一部分。 加强件可以具有下降部分。 散热片可以附着在加强件的暴露部分上。 可以使用锁定机构来增强热块与加强件的连接。 热芯可以通过加强件中的开口直接附接到模具。

公开(公告)号：US5765761A

公开(公告)日：1998-06-16

申请号：US506725

申请日：1995-07-26

Applicant: S. Edward Law ,  Steven C. Cooper

Inventor： S. Edward Law ,  Steven C. Cooper

IPC: B05B5/03 ,  B05B5/043 ,  B05B5/053 ,  B05B5/16 ,  B05B5/43

CPC classification number: B05B5/043 ,  B05B5/03 ,  B05B5/0533 ,  B05B5/1608

Abstract: The disclosed invention relates to electrostatic spraying systems for liquids and specifically to an improved spray-charging nozzle system having increased reliability, consistency, safety and power efficiency for long-term operation in harsh agricultural and industrial applications. The invention achieves these advantages by: a) management of the interaction of any externally-originating electric fields with the droplet-charging electric-induction field being applied within the nozzle, including partial or total exclusion of the former fields; b) maintenance of the charge-induction electric field at the droplet-formation zone by precluding or minimizing leakage of charge in all directions from the induction electrode; c) protection of electronic and nozzle components from damage due to inadvertent overcurrents; and d) facilitation of non-tedious, convenient, trouble-free inspection and cleaning of the nozzle under harsh field conditions.

Abstract translation: 所公开的发明涉及用于液体的静电喷涂系统，特别涉及一种改进的喷雾充气喷嘴系统，其具有在苛刻的农业和工业应用中长期运行的可靠性，一致性，安全性和功率效率。 本发明通过以下方式实现了这些优点：a）管理任何外部产生的电场与在喷嘴内施加的液滴充电感应场的相互作用，包括部分或全部排除前者; b）通过排除或最小化来自感应电极的各个方向的电荷泄漏来维持液滴形成区的电荷感应电场; c）保护电子和喷嘴部件免受由于无意的过电流的损坏; 以及d）在苛刻的野外条件下，方便无暇，方便，无故障地检查和清洁喷嘴。

公开(公告)号：US4685620A

公开(公告)日：1987-08-11

申请号：US781487

申请日：1985-09-30

Applicant: S. Edward Law ,  Henry D. Bowen

Inventor： S. Edward Law ,  Henry D. Bowen

IPC: A01N25/06 ,  B05B5/08 ,  B05D1/04 ,  B05D1/06 ,  A01N25/08

CPC classification number: B05D1/04 ,  A01N25/06 ,  B05B5/08

Abstract: A method for increasing the efficiency of electrostatic deposition of particulate matter on a surface, which comprises preparing a dispersion of electrostatically charged particles of an active material to be deposited on the surface, wherein the particles of active material have an average radius of r.sub.p1 and a total volume of V.sub.L1, in a space adjacent to the surface which contains a dispersion of particles of an inert material, electrostatically charged with the same polarity as said particles of active material, wherein the particles of inert material have an average radius of r.sub.p2 and a total volume of V.sub.L2, wherein r.sub.p1 >r.sub.p2 and ##STR1##

Abstract translation: 一种用于提高颗粒物质在表面上的静电沉积效率的方法，其包括制备要沉积在表面上的活性材料的静电荷颗粒的分散体，其中活性材料颗粒具有平均半径rp1和 VL1的总体积在与包含惰性材料的颗粒的分散体的表面相邻的空间中，静电充电与所述活性材料颗粒相同，其中惰性材料颗粒的平均半径为rp2，并且 VL2的总体积，其中rp1> rp2和

公开(公告)号：US08367475B2

公开(公告)日：2013-02-05

申请号：US13071799

申请日：2011-03-25

Applicant: Edward Law ,  Rezaur R. Khan ,  Edmund Law

Inventor： Edward Law ,  Rezaur R. Khan ,  Edmund Law

IPC: H01L21/00

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/13 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Methods, systems, and apparatuses are described for the assembly of integrated circuit (IC) packages. A substrate panel is formed that includes a plurality of substrates. The substrate panel is singulated to separate the plurality of substrates. At least a subset of the separated substrates is attached to a surface of a carrier. One or more dies are attached to each of the substrates on the carrier. The dies and the substrates are encapsulated on the carrier with a molding compound. The carrier is detached from the encapsulated dies and substrates to form a molded assembly that includes the molding compound encapsulating the dies and substrates. A plurality of interconnects is attached to each of the substrates at a surface of the molded assembly. The molded assembly is singulated to form a plurality of IC packages. Each IC package includes at least one of the dies and a substrate.

Abstract translation: 描述了用于组装集成电路（IC）封装的方法，系统和装置。 形成包括多个基板的基板。 单个基板面板以分离多个基板。 分离的衬底的至少一个子集附着到载体的表面。 一个或多个管芯附着到载体上的每个基底上。 模具和基材用模塑料包封在载体上。 载体与封装的模具和基板分离以形成模制组件，其包括封装模具和基板的模塑料。 在模制组件的表面处，将多个互连件连接到每个基板。 将模制组件分割成多个IC封装。 每个IC封装包括至少一个裸片和衬底。

公开(公告)号：US08088647B2

公开(公告)日：2012-01-03

申请号：US12783855

申请日：2010-05-20

Applicant: Kunzhong (Kevin) Hu ,  Edward Law

Inventor： Kunzhong (Kevin) Hu ,  Edward Law

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/00

CPC classification number: H01L23/3128 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: Methods, systems, and apparatuses for an integrated circuit package assembly process are provided. A wafer is received having a surface defined by a plurality of integrated circuit regions. Electrical conductors are accessible through corresponding first openings in a first passivation layer on the surface of the wafer. Solderable metal layer features are formed on the electrical conductors through the first openings. The wafer is singulated to form a plurality of flip chip dies. A plurality of package substrates is received. Each package substrate has a plurality of solder on pad (SOP) features on a respective surface. Each flip chip die is mounted to a corresponding package substrate such that each SOP feature is coupled to a corresponding solderable metal layer feature, to form a plurality of integrated circuit packages.

Abstract translation: 提供了用于集成电路封装组装过程的方法，系统和装置。 接收具有由多个集成电路区域限定的表面的晶片。 电导体可通过晶片表面上的第一钝化层中相应的第一开口进入。 可焊接金属层特征通过第一开口形成在电导体上。 将晶片分离以形成多个倒装芯片管芯。 接收多个封装基板。 每个封装衬底在相应的表面上具有多个衬垫焊接（SOP）特征。 每个倒装芯片管芯安装到相应的封装衬底，使得每个SOP特征耦合到相应的可焊接金属层特征，以形成多个集成电路封装。