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    Circuit structure for a memory matrix and corresponding manufacturing method
    1.
    发明授权
    Circuit structure for a memory matrix and corresponding manufacturing method 失效
    存储矩阵的电路结构及相应的制造方法

    公开(公告)号：US5677871A

    公开(公告)日：1997-10-14

    申请号：US688233

    申请日：1996-07-29

    申请人： Federico Pio ,  Carlo Riva ,  Silvia Lucherini

    发明人： Federico Pio ,  Carlo Riva ,  Silvia Lucherini

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11526 ,  G11C16/04 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11541

    摘要： A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells including plural rows and columns, with each row being provided with a word line and a control gate line and each column having a bit line; the bit lines, moreover, are gathered into groups or bytes of simultaneously addressable adjacent lines. Each cell in the matrix incorporates a floating gate transistor which is coupled to a control gate, connected to the control gate line, and is connected serially to a selection transistor; also, the cells of each individual byte share their respective source areas, which areas are structurally independent for each byte and are led to a corresponding source addressing line extending along a matrix column.

    摘要翻译： 一种用于EEPROM存储器单元的矩阵的电路结构，其包括包括多行和列的单元矩阵，每行具有字线和控制栅极线，每列具有位线; 此外，位线被收集成同时可寻址的相邻线的组或字节。 矩阵中的每个单元都包含一个浮动栅极晶体管，它连接到控制栅极，连接到控制栅极线，并串联连接到选择晶体管; 每个单独字节的单元也共享它们各自的源区域，哪些区域对于每个字节在结构上是独立的，并且被引导到沿着矩阵列延伸的对应的源寻址行。

    Method of manufacturing double polysilicon EEPROM cell and access transistor
    4.
    发明授权
    Method of manufacturing double polysilicon EEPROM cell and access transistor 失效
    制造双晶硅EEPROM单元和存取晶体管的方法

    公开(公告)号：US5792670A

    公开(公告)日：1998-08-11

    申请号：US475671

    申请日：1995-06-06

    申请人： Federico Pio ,  Carlo Riva

    发明人： Federico Pio ,  Carlo Riva

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A method for programming a two-level polysilicon EEPROM memory cell, which cell is implemented in MOS technology on a semiconductor substrate and comprises a floating gate transistor and a further control gate overlying the floating gate with a dielectric layer therebetween, provides for the application of a negative voltage to the control gate during the cell write phase. This enables the voltages being applied across the thin tunnel oxide layer to be distributed so as to reduce the maximum amount of energy of the "holes" and improve the oxide reliability. In addition, by controlling the rise speed of the impulse to the drain region during the write phase, and of the impulse to the control gate during the erase phase, the maximum current flowing through the tunnel oxide can be set and the electric field being applied to the tunnel oxide kept constant, thereby the device life span can be extended.

    摘要翻译： 一种用于编程两电平多晶硅EEPROM存储单元的方法，该单元在半导体衬底上的MOS技术中实现，并且包括浮置栅晶体管和覆盖浮置栅极的其它控制栅极，其间具有介电层， 在单元写入阶段期间向控制栅极施加负电压。 这使得施加在薄隧道氧化物层上的电压被分布，以便减少“孔”的最大能量并提高氧化物的可靠性。 此外，通过在写入阶段期间控制到漏极区域的脉冲的上升速度以及在擦除阶段期间对控制栅极的脉冲的上升速度，可以设定流过隧道氧化物的最大电流并施加电场 隧道氧化物保持恒定，从而可延长设备使用寿命。

    Double polysilicon EEPROM cell and corresponding manufacturing process and programming method
    6.
    发明授权
    Double polysilicon EEPROM cell and corresponding manufacturing process and programming method 失效
    双晶多晶硅EEPROM单元及相应的制造工艺及编程方法

    公开(公告)号：US5793673A

    公开(公告)日：1998-08-11

    申请号：US914518

    申请日：1997-08-19

    申请人： Federico Pio ,  Carlo Riva

    发明人： Federico Pio ,  Carlo Riva

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34 ,  H01L29/68

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A method for programming a two-level polysilicon EEPROM memory cell, which cell is implemented in MOS technology on a semiconductor substrate and comprises a floating gate transistor and a further control gate overlying the floating gate with a dielectric layer therebetween, provides for the application of a negative voltage to the control gate during the cell write phase. This enables the voltages being applied across the thin tunnel oxide layer to be distributed so as to reduce the maximum amount of energy of the "holes" and improve the oxide reliability. In addition, by controlling the rise speed of the impulse to the drain region during the write phase, and of the impulse to the control gate during the erase phase, the maximum current flowing through the tunnel oxide can be set and the electric field being applied to the tunnel oxide kept constant, thereby the device life span can be extended.

    摘要翻译： 一种用于编程两电平多晶硅EEPROM存储单元的方法，该单元在半导体衬底上的MOS技术中实现，并且包括浮置栅晶体管和覆盖浮置栅极的其它控制栅极，其间具有介电层， 在单元写入阶段期间向控制栅极施加负电压。 这使得施加在薄隧道氧化物层上的电压被分布，以便减少“孔”的最大能量并提高氧化物的可靠性。 此外，通过在写入阶段期间控制到漏极区域的脉冲的上升速度以及在擦除阶段期间对控制栅极的脉冲的上升速度，可以设定流过隧道氧化物的最大电流并施加电场 隧道氧化物保持恒定，从而可延长设备使用寿命。

    HV transistor structure and corresponding manufacturing method
    8.
    发明授权
    HV transistor structure and corresponding manufacturing method 有权
    HV晶体管结构及相应的制造方法

    公开(公告)号：US06278163B1

    公开(公告)日：2001-08-21

    申请号：US09224939

    申请日：1998-12-31

    申请人： Federico Pio ,  Carlo Riva

    发明人： Federico Pio ,  Carlo Riva

    IPC分类号： H01L31062

    CPC分类号： H01L29/66575 ,  H01L21/823418 ,  H01L21/823443 ,  H01L27/088 ,  H01L27/105 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/7833

    摘要： An HV transistor integrated in a semiconductor substrate with a first type of conductivity, comprising a gate region included between corresponding drain and source regions, and being of the type wherein at least said drain region is lightly doped with a second type of conductivity. The drain region comprises a contact region with the second type of conductivity but being more heavily doped, from which a contact pad extends.

    摘要翻译： 集成在具有第一类型导电性的半导体衬底中的HV晶体管，包括在相应的漏极和源极区域之间包括的栅极区域，并且其中至少所述漏极区域被轻掺杂第二类型的导电性。 漏极区域包括具有第二类型导电性的接触区域，但是其重新掺杂，接触焊盘从该区域延伸。

    Method of manufacturing a matrix of memory cells having control gates
    9.
    发明授权
    Method of manufacturing a matrix of memory cells having control gates 失效
    具有控制门的存储器单元的矩阵的制造方法

    公开(公告)号：US5597750A

    公开(公告)日：1997-01-28

    申请号：US474735

    申请日：1995-06-07

    申请人： Federico Pio ,  Carlo Riva ,  Silvia Lucherini

    发明人： Federico Pio ,  Carlo Riva ,  Silvia Lucherini

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11526 ,  G11C16/04 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11541

    摘要： A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells including plural rows and columns, with each row being provided with a word line and a control gate line and each column having a bit line; the bit lines, moreover, are gathered into groups or bytes of simultaneously addressable adjacent lines. Each cell in the matrix incorporates a floating gate transistor which is coupled to a control gate, connected to the control gate line, and is connected serially to a selection transistor; also, the cells of each individual byte share their respective source areas, which areas are structurally independent for each byte and are led to a corresponding source addressing line extending along a matrix column.

    摘要翻译： 一种用于EEPROM存储器单元的矩阵的电路结构，其包括包括多行和列的单元矩阵，每行具有字线和控制栅极线，每列具有位线; 此外，位线被收集成同时可寻址的相邻线的组或字节。 矩阵中的每个单元都包含一个浮动栅极晶体管，它连接到控制栅极，连接到控制栅极线，并串联连接到选择晶体管; 每个单独字节的单元也共享它们各自的源区域，哪些区域对于每个字节在结构上是独立的，并且被引导到沿着矩阵列延伸的对应的源寻址行。