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    PHASE SPLITTER USING DIGITAL DELAY LOCKED LOOPS
    1.
    发明申请
    PHASE SPLITTER USING DIGITAL DELAY LOCKED LOOPS 失效
    使用数字延迟锁定的相位分离器

    公开(公告)号：US20110102036A1

    公开(公告)日：2011-05-05

    申请号：US12987431

    申请日：2011-01-10

    Applicant: Feng Lin ,  R. Jacob Baker

    Inventor： Feng Lin ,  R. Jacob Baker

    IPC: H03L7/00 ,  H03K5/13

    CPC classification number: H03L7/0805 ,  H03K5/15013 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/089

    Abstract: A phase splitter uses digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.

    Abstract translation: 分相器使用数字延迟锁定环（DLL）来接收互补输入时钟信号以产生具有不同相移的多个输出信号。 当DLL被锁定时，分相器的延迟分辨率等于DLL的两个延迟级。

    Digital dual-loop DLL design using coarse and fine loops
    3.
    发明授权
    Digital dual-loop DLL design using coarse and fine loops 失效
    数字双环DLL设计使用粗细和细循环

    公开(公告)号：US06774690B2

    公开(公告)日：2004-08-10

    申请号：US10208060

    申请日：2002-07-30

    Applicant: R. Jacob Baker ,  Feng Lin

    Inventor： R. Jacob Baker ,  Feng Lin

    IPC: H03L706

    CPC classification number: G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0818

    Abstract: A dual-loop digital delay locked loop (DLL) is provided. The DLL includes a coarse loop to produce a first delayed signal and provides a wide frequency lock range. The DLL further includes a fine loop connected to the coarse loop to produce a second delayed signal and provides a tight locking. This dual-loop architecture can provide robust operation and tight synchronization over a wide range of delay variations.

    Abstract translation: 提供了一个双回路数字延迟锁定环（DLL）。 该DLL包括粗回路以产生第一延迟信号并提供宽频率锁定范围。 DLL还包括连接到粗回路的精细回路以产生第二延迟信号并且提供紧密锁定。 这种双回路架构可以在广泛的延迟变化范围内提供稳健的操作和紧密的同步。

    Phase detector for all-digital phase locked and delay locked loops
    4.
    发明授权
    Phase detector for all-digital phase locked and delay locked loops 失效
    全数字锁相和延迟锁定环路的相位检测器

    公开(公告)号：US06987701B2

    公开(公告)日：2006-01-17

    申请号：US10862807

    申请日：2004-06-07

    Applicant: Feng Lin ,  R. Jacob Baker

    Inventor： Feng Lin ,  R. Jacob Baker

    IPC: G11C7/00

    CPC classification number: G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/0995 ,  H03L2207/50

    Abstract: A phase detector is comprised of two cross-coupled gates which are capable of phase discrimination down to a level of approximately 10 picoseconds. An arbiter circuit, responsive to the cross-coupled gates, generates mutually exclusive UP and DOWN pulse signals. The UP and DOWN pulse signals may be filtered and used to control the delay line of an all digital delay locked or phase locked loop.

    Abstract translation: 相位检测器由两个交叉耦合的栅极组成，它们能相位分辨到大约10皮秒的水平。 响应于交叉耦合门的仲裁电路产生互斥的UP和DOWN脉冲信号。 UP和DOWN脉冲信号可以被滤波并用于控制全数字延迟锁定或锁相环的延迟线。

    Digital dual-loop DLL design using coarse and fine loops
    6.
    发明授权
    Digital dual-loop DLL design using coarse and fine loops 有权
    数字双环DLL设计使用粗细和细循环

    公开(公告)号：US06445231B1

    公开(公告)日：2002-09-03

    申请号：US09585035

    申请日：2000-06-01

    Applicant: R. Jacob Baker ,  Feng Lin

    Inventor： R. Jacob Baker ,  Feng Lin

    IPC: H03D324

    CPC classification number: G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0818

    Abstract: A dual-loop digital delay locked loop (DLL) is provided. The DLL includes a coarse loop to produce a first delayed signal and provides a wide frequency lock range. The DLL further includes a fine loop connected to the coarse loop to produce a second delayed signal and provides a tight locking. This dual-loop architecture can provide robust operation and tight synchronization over a wide range of delay variations.

    Abstract translation: 提供了一个双回路数字延迟锁定环（DLL）。 该DLL包括粗回路以产生第一延迟信号并提供宽频率锁定范围。 DLL还包括连接到粗回路的精细回路以产生第二延迟信号并且提供紧密锁定。 这种双回路架构可以在广泛的延迟变化范围内提供稳健的操作和紧密的同步。

    Phase splitter using digital delay locked loops
    7.
    发明授权
    Phase splitter using digital delay locked loops 失效
    分相器使用数字延迟锁定环路

    公开(公告)号：US08218708B2

    公开(公告)日：2012-07-10

    申请号：US12987431

    申请日：2011-01-10

    Applicant: Feng Lin ,  R. Jacob Baker

    Inventor： Feng Lin ,  R. Jacob Baker

    IPC: H03D3/24

    CPC classification number: H03L7/0805 ,  H03K5/15013 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/089

    Abstract: A phase splitter uses digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.

    Abstract translation: 分相器使用数字延迟锁定环（DLL）来接收互补输入时钟信号以产生具有不同相移的多个输出信号。 当DLL被锁定时，分相器的延迟分辨率等于DLL的两个延迟级。

    Phase splitter using digital delay locked loops
    8.
    发明授权
    Phase splitter using digital delay locked loops 有权
    分相器使用数字延迟锁定环路

    公开(公告)号：US07873131B2

    公开(公告)日：2011-01-18

    申请号：US11216778

    申请日：2005-08-31

    Applicant: Feng Lin ,  R. Jacob Baker

    Inventor： Feng Lin ,  R. Jacob Baker

    IPC: H03D3/24

    CPC classification number: H03L7/0805 ,  H03K5/15013 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/089

    Abstract: A phase splitter using digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.

    Abstract translation: 一种使用数字延迟锁定环（DLL）来接收互补输入时钟信号以产生具有不同相移的多个输出信号的分相器。 当DLL被锁定时，分相器的延迟分辨率等于DLL的两个延迟级。

    Phase detector for all-digital phase locked and delay locked loops
    9.
    发明授权
    Phase detector for all-digital phase locked and delay locked loops 有权
    全数字锁相和延迟锁定环路的相位检测器

    公开(公告)号：US06779126B1

    公开(公告)日：2004-08-17

    申请号：US09652364

    申请日：2000-08-31

    Applicant: Feng Lin ,  R. Jacob Baker

    Inventor： Feng Lin ,  R. Jacob Baker

    IPC: G06F104

    CPC classification number: G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/0995 ,  H03L2207/50

    Abstract: A phase detector is comprised of two cross-coupled gates which are capable of phase discrimination down to a level of approximately 10 picoseconds. An arbiter circuit, responsive to the cross-coupled gates, generates mutually exclusive UP and DOWN pulse signals. The UP and DOWN pulse signals may be filtered and used to control the delay line of an all digital delay locked or phase locked loop. Methods of operation are also disclosed.

    Abstract translation: 相位检测器由两个交叉耦合的栅极组成，它们能相位分辨到大约10皮秒的水平。 响应于交叉耦合门的仲裁电路产生互斥的UP和DOWN脉冲信号。 UP和DOWN脉冲信号可以被滤波并用于控制全数字延迟锁定或锁相环的延迟线。 还公开了操作方法。

    Beach mesh bag
    10.
    外观设计
    Beach mesh bag 有权

    公开(公告)号：USD1059030S1

    公开(公告)日：2025-01-28

    申请号：US29951703

    申请日：2024-07-11

    Applicant: Feng Lin

    Designer： Feng Lin

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